Modelling of 14NM Gate Length La2O3 -based n-Type MOSFET

Authors

  • S.K. Mah Department of Electrical Engineering, Faculty of Engineering, Nilai University, 71800 Nilai, Negeri Sembilan, Malaysia
  • I. Ahmad Centre for Micro and Nano Engineering (CeMNE), Universiti Tenaga Nasional (UNITEN), 43009 Kajang, Selangor, Malaysia
  • P.J. Ker Centre for Micro and Nano Engineering (CeMNE), Universiti Tenaga Nasional (UNITEN), 43009 Kajang, Selangor, Malaysia
  • Noor Faizah Z.A. Centre for Micro and Nano Engineering (CeMNE), Universiti Tenaga Nasional (UNITEN), 43009 Kajang, Selangor, Malaysia

Keywords:

14nm n-transistor, High-k dielectric, Metal Gate, ATHENA, ATLAS,

Abstract

Gate length shrinkage is still the widely used method in transistor downsizing. In view of this, the downsizing of Equivalent Oxide Thickness (EOT) is also of high importance as it is the main focus in the process. Therefore, various studies on Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) fabricated from high-k dielectric and metal gate have been reported till today. In this paper, a 14nm silicon based n-type MOSFET was virtually fabricated using Lanthanum Oxide (La2O3) on Titanium Silicide (TiSi2). ATHENA and ATLAS modules from SILVACO were used for process and device simulation respectively. The results from this work show that the threshold voltage, VTH, on-current, ION and offcurrent, IOFF are 0.208397 V, 4.80048 x 10-5 A/µm and 1.00402 x 10-7 A/µm respectively. Furthermore, it is demonstrated that the development of high-k/metal gate MOSFET is a promising prospect for high performance nanoscale transistors.

Downloads

Published

2016-07-01

How to Cite

Mah, S., Ahmad, I., Ker, P., & Z.A., N. F. (2016). Modelling of 14NM Gate Length La2O3 -based n-Type MOSFET. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 8(4), 107–110. Retrieved from https://jtec.utem.edu.my/jtec/article/view/1182

Most read articles by the same author(s)

1 2 > >>