Process Parameter Optimisation for Minimum Leakage Current in a 22nm p-type MOSFET using Taguchi Method

Abstract

In this research paper, the effects of variation on the process parameters were optimised while designing a nano-scaled p-type MOSFET (metal-oxide-semiconductor field-effect transistor) planar device for 22 nm technology. The aim of this procedure is to meet the minimum leakage current (IOFF) by optimising the process parameters as leakage current. It is one of the characteristics that must be taken into account for device functionality. The gate structure of the device consists of Titanium dioxide (TiO2) that functions as the high permittivity material (high-k) dielectric and Tungsten silicide (WSix) metal gate, where it is deposited on top of the TiO2 high-k layer. The fabrication process was designed using an industrial-based numerical simulator. This simulator was then aided in design with the L9 Taguchi’s orthogonal array method to optimise the process parameters to achieve the best combination of the process parameters with the lowest leakage current. The objective is to obtain IOFF values using Smaller-the-Better (STB) signal-to-noise ratio (SNR). The results of the factor effect on the SNR clearly shows that the Halo implantation tilting angle has the greatest influence with 52.47% in minimising the leakage current of the device where the implantation tilting angle is 35°. It is followed by the Halo implantation dose with 34.23% effect, gate oxide growth annealing temperature was ranked third at 12.29% effect and metal gate annealing temperature has the least influence with 1.01%. The final results in characterising and modelling the process parameters of the 22nm PMOS device technology with reference to the prediction by the International Technology Roadmap for Semiconductors (ITRS) succeeded, where the result of the IOFF value was lower than the predicted value which is less than 100 nA/µm.