Process Parameters Optimization of 14 nm p-Type MOSFET using 2-D Analytical Modeling

Authors

  • Noor Faizah Z.A. Centre for Micro and Nano Engineering (CeMNE), Universiti Tenaga Nasional (UNITEN), 43009 Kajang, Selangor, Malaysia.
  • I. Ahmad Centre for Micro and Nano Engineering (CeMNE), Universiti Tenaga Nasional (UNITEN), 43009 Kajang, Selangor, Malaysia.
  • P.J. Ker Centre for Micro and Nano Engineering (CeMNE), Universiti Tenaga Nasional (UNITEN), 43009 Kajang, Selangor, Malaysia.
  • Siti Munirah Y. Centre for Micro and Nano Engineering (CeMNE), Universiti Tenaga Nasional (UNITEN), 43009 Kajang, Selangor, Malaysia.
  • Mohd Firdaus R. Centre for Micro and Nano Engineering (CeMNE), Universiti Tenaga Nasional (UNITEN), 43009 Kajang, Selangor, Malaysia.
  • S.K. Mah Centre for Micro and Nano Engineering (CeMNE), Universiti Tenaga Nasional (UNITEN), 43009 Kajang, Selangor, Malaysia.
  • P.S. Menon Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia (UKM), 43600 Bangi, Selagor, Malaysia.

Keywords:

14 nm p-type MOSFET, High-k Dielectric, Silvaco, Taguchi method,

Abstract

Simulations of a computer-generated downscaled device at 14nm gate length of p-type MOSFET is conferred in this paper. The device is scaled down from a 32nm transistor which is from the former research. A combination of insulatorconductor that were used includes a high-k material and a metalgate where in this research, Hafnium Dioxide (HfO2) is used as high-k material and Tungsten Silicide (WSi2) is used as a metal gate. A 14nm p-type transistor was virtually fabricated usingATHENA module and characterized its performance evaluation using ATLAS module in Virtual Wafer Fabrication (VWF) of Silvaco TCAD Tools. The scaled down device is then optimized through process parameter variability using Taguchi Method. The objective is to find the best combination of fabrication parameter in order to achieve the targeted value of threshold voltage (VTH) and leakage current (IOFF) that are predicted by International Technology Roadmap for Semiconductors (ITRS) 2013. The results show that the ideal value for VTH and IOFF are 0.248635±12.7% V and 5.26x10-12A/um respectively and the results were achieved according to the ITRS specification.

References

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Published

2016-07-01

How to Cite

Z.A., N. F., Ahmad, I., Ker, P., Y., S. M., R., M. F., Mah, S., & Menon, P. (2016). Process Parameters Optimization of 14 nm p-Type MOSFET using 2-D Analytical Modeling. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 8(4), 97–100. Retrieved from https://jtec.utem.edu.my/jtec/article/view/1180

Issue

Vol. 8 No. 4: Pioneering Future Innovation Through Green Technology II

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Articles

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