Statistical Modelling of 14nm N-types MOSFET

Authors

  • Noor Faizah Z.A. Centre for Micro and Nano Engineering (CeMNE), Universiti Tenaga Nasional (UNITEN), 43009 Kajang, Selangor, Malaysia
  • I. Ahmad Centre for Micro and Nano Engineering (CeMNE), Universiti Tenaga Nasional (UNITEN), 43009 Kajang, Selangor, Malaysia
  • P.J. Ker Centre for Micro and Nano Engineering (CeMNE), Universiti Tenaga Nasional (UNITEN), 43009 Kajang, Selangor, Malaysia
  • Siti Munirah Y. Centre for Micro and Nano Engineering (CeMNE), Universiti Tenaga Nasional (UNITEN), 43009 Kajang, Selangor, Malaysia
  • Mohd Firdaus R. Centre for Micro and Nano Engineering (CeMNE), Universiti Tenaga Nasional (UNITEN), 43009 Kajang, Selangor, Malaysia
  • S.K. Mah Centre for Micro and Nano Engineering (CeMNE), Universiti Tenaga Nasional (UNITEN), 43009 Kajang, Selangor, Malaysia
  • P.S. Menon Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia (UKM), 43600 Bangi, Selagor, Malaysia

Keywords:

14 nm n-type MOSFET, High k-dielectric, Silvaco TCAD Tools, Taguchi Method,

Abstract

This paper focuses on virtual modelling and optimization of 14nm n-types planar MOSFET. Here, high-k dielectric and metal gate were used where the high-k material is Hafnium Dioxide (HfO2) and the metal gate is Tungsten Silicide (WSi2). 36 simulations of Taguchi L9 Orthogonal Array method were applied in order to obtain the best parameter design for optimization of both performance parameters which are threshold voltage (VTH) and leakage current (IOFF). The simulation and fabrication for n-type transistor was conducted through Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools named ATHENA and ATLAS for its electrical characterization. For analyzation of the impact parameters on VTH and IOFF, two noise parameters and four process parameters value were varied. From the simulations, the results show the best value were well within ITRS prediction where VTH and IOFF are 0.236737 V and 6.995705 nA/um respectively

References

H.A. Elgomathi, B. Yeop Majlis, F. Salehuddin, I. Ahmad, A, Zaharim, F.A. Hamid,“Optimizing 35nm NMOS Devices Vth and Ileak by Controlling Active Area and Halo Implantation Dosage,” RSM2011 Proc., pp. 286-290, 2011.

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Published

2016-07-01

How to Cite

Z.A., N. F., Ahmad, I., Ker, P., Y., S. M., R., M. F., Mah, S., & Menon, P. (2016). Statistical Modelling of 14nm N-types MOSFET. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 8(4), 91–95. Retrieved from https://jtec.utem.edu.my/jtec/article/view/1179

Issue

Vol. 8 No. 4: Pioneering Future Innovation Through Green Technology II

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Articles

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