Control Factors Optimization on Threshold Voltage and Leakage Current in 22 nm NMOS Transistor Using Taguchi Method

Authors

  • Afifah Maheran A.H. CeTRI, Faculty of Electronics & Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka (UTeM), Hang Tuah Jaya, 76100 Durian Tunggal, Melaka.
  • Menon P.S. IMEN, Universiti Kebangsaan Malaysia (UKM), 43600 Bangi, Selangor.
  • I. Ahmad CeMNE, College of Engineering, Universiti Tenaga Nasional (UNITEN), 43009 Kajang, Selangor.
  • F. Salehuddin CeTRI, Faculty of Electronics & Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka (UTeM), Hang Tuah Jaya, 76100 Durian Tunggal, Melaka.
  • A.S. Mohd Zain CeTRI, Faculty of Electronics & Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka (UTeM), Hang Tuah Jaya, 76100 Durian Tunggal, Melaka.
  • Noor Faizah Z. A. CeMNE, College of Engineering, Universiti Tenaga Nasional (UNITEN), 43009 Kajang, Selangor.
  • H.A. Elgomati IMEN, Universiti Kebangsaan Malaysia (UKM), 43600 Bangi, Selangor. Faculty of Engineering Technology, 34000 Janzour, Libya.

Keywords:

22 Nm NMOS Tio2/Wsix, High-K/Metal Gate, Threshold Voltage, Leakage Current, Taguchi Method,

Abstract

In this article, Taguchi method was used to optimize the control factor in obtaining the optimal value which is also known as response characteristics, where the threshold voltage (Vth) and leakage current (Ileak) for NMOS transistor with a gate length of 22 nm is taken into account. The NMOS transistor design includes a high permittivity material (high-k) as a dielectric layer and a metal gate which is Titanium Dioxide (TiO2) and Tungsten Silicide (WSiX) respectively. The control factor was optimized in designing the NMOS device using the Taguchi Orthogonal Array Method where the Signal-to-Noise Ratio (SNR) analysis uses the Nominal-the-Best (NTB) SNR for Vth, while for Ileak analysis, a Smaller-the-Better (STB) SNR was used. Four manufacturing control factors and two noise factor are used to optimize the response characteristics and find the best combination of design parameters. The results show that the Halo implantation tilting angle is the dominant factor where it has the greatest factor effect on the SNR of the Ileak with 55.52%. It is also shown that the values of Vth have the least variance and the mean value can be set to 0.289 V ± 12.7% and Ileak is less than 100 nA/µm which is in line with the projections made by the International Technology Roadmap for Semiconductors (ITRS).

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Published

2017-09-01

How to Cite

A.H., A. M., P.S., M., Ahmad, I., Salehuddin, F., Mohd Zain, A., Z. A., N. F., & Elgomati, H. (2017). Control Factors Optimization on Threshold Voltage and Leakage Current in 22 nm NMOS Transistor Using Taguchi Method. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 9(2-7), 137–141. Retrieved from https://jtec.utem.edu.my/jtec/article/view/2610

Issue

Vol. 9 No. 2-7: Towards Creative and Innovative Technologies for Humankind I

Section

Articles

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