VTH and ILEAK Optimization Using Taguchi Method at 32nm Bilayer Graphene PMOS

Abstract

A 32nm top-gated bilayer Graphene PMOS transistor was optimized and analyzed to find the optimum value of performance parameters besides investigating the process parameter that affects the performance of the bilayer Graphene transistor the most. Firstly, ATHENA and ATLAS modules which can be found in Silvaco TCADS Tools were employed to simulate the virtual device fabrication process and to confirm the electrical features of the device, respectively. L9 Taguchi robust analysis was then applied to enhance the device process parameters for the finest threshold voltage (VTH) and lowest leakage current (ILEAK) following the International Technology Roadmap for Semiconductor (ITRS) 2011 prediction. The parameters being optimized were the Halo implantation, Halo tilting angle, S/D implantation and compensation implantation which were varied at three levels and two levels of noise factor. The noise factors include sacrificial oxide layer temperature and BPSG temperature. The results of this work show that compensation implantation and Halo implantation are the most dominant factors in affecting the VTH and ILEAK respectively. Optimized results show an excellent device performance with VTH of -0.10299V which is 0.0097% closer to ITRS2011 target and ILEAK is 0.05545673nA/um which is far lower than the prediction.