Analyze Of Process Parameter Variance In 19nm Wsi2/Tio2 NMOS Device Using 2k-Factorial Design

Authors

  • F. Salehuddin Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka
  • Ameer F. Roslan Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka
  • A.E. Zailan Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka
  • K.E. Kaharudin Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka
  • A.S.M. Zain Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka
  • Afifah Maheran A.H. Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka
  • A.R. Hanim Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka
  • H. Hazura Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka
  • S.K. Idris Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka
  • Wira Hidayat Mohd Saad Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka

Keywords:

2k-factorial Design, Ion implantation, NMOS Device,

Abstract

This project investigates and analyzes the impact of process parameter variance on the drive current (ION) and leakage current (IOFF) for 19nm WSi2/TiO2 NMOS device using 2k-factorial design. The four process parameter, namely halo implant dose, halo implant energy, source/drain (S/D) implant dose and S/D implant energy will be investigated and adjusted to improve the results. The simulated of the device was performed by using ATHENA module. Meanwhile the electrical characterization of the device was implemented by using ATLAS module. These two modules will be combined with 2kfactorial to aid design and optimize the process parameters. The most effective process parameter with respect ION and IOFF were chosen depending on the percentage of the factor effect on S/N ratio that indicates the relative power of factor to reduce variation. The most dominant or significant factors in S/N Ratio are pocket halo implant dose and S/D implant energy. Meanwhile, the values of ION and IOFF values for 19nm WSi2/SiO2 NMOS device after optimization approaches are 591.38 µA/µm and 2.217 pA/µm respectively. The results obtained are meet the requirement of International Technology Roadmap Semiconductor (ITRS) 2013 prediction.

References

V. K. Yadav and A. K. Rana, “Impact of Channel Doping on DGMOSFET Parameters in Nano Regime-TCAD Simulation,” Int. J. Comput. Appl., vol. 37, no. 11, pp. 36–41, 2012.

Q. Xu, et. al., “Ion-Implanted TiN Metal Gate With Dual Band-Edge Work Function and Excellent Reliability for Advanced CMOS Device Applications,” IEEE Trans. Electron Devices, vol. 62, no. 12, pp. 4199–4205, 2015.

S.Lokman, et. al., “Performance analysis of 19nm n-channel MOSFET device with high-k dielectric materials”, In Proceeding of Mechanical Research Day 2017, pp. 86-87, March 2017.

N.B.Atan, I.Ahmad, B.Y.Majlis, and A.Fauzi, “Effects of High-K Dielectric with Metal Gate for Electrical Characteristics of Nanostructured NMOS,” pp. 111–115.

Afifah Maheran A.H., et.al., “Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor” Journal of Physics: Conference Series, vol. 431, no. 1, pp. 021-026, 2013

F. Salehuddin, I. Ahmad, F. Hamid and A. Zaharim, “Effect of process parameter variations on threshold voltage in 45nm NMOS device”, 2010 IEEE Student Conference on Research and Development (SCOReD), pp. 334-338, 2010.

H. Elgomati et. al., “Statistical Optimization for process parameters to reduce variability of 32 nm PMOS transistor Threshold voltage”, International Journal of the Physical Sciences, vol. 6, no. 10, pp. 2372- 2379, 2011.

F.Salehuddin, K.E.Kaharudin, H.A.Elgomati, I. Ahmad, P. R. Apte, Z. M. Nopiah, A. Zaharim, “Comparison of 2k-Factorial and Taguchi Method for Optimization Approach in 32nm NMOS Device”, Mathematical Methods and Optimization Techniques in Engineering, pp. 125-134, 2013.

ITRS, “International Technology Roadmap Semiconductor,” 2013.

M.N.I.A.Aziz, F.Salehuddin, A.S.M.Zain, K.E.Kaharudin and S.A.Radzi, “Comparison of electrical characteristics between Bulk MOSFET and Silicon-on-insulator (SOI) MOSFET”, Journal of Telecommunication, Electronic and Computer Engineering, vol. 6, no. 2, pp. 45-49, 2014.

Afifah Maheran A.H. et. al., “Design and Optimization of 22nm NMOS Transistor”. Australian Journal of Basic and Applied Sciences, ISSN 1991-8178, Vol. 6, No. 7, pp. 1-8, 2012.

A.K. Goel, M. Merry, K. Arkenberg, E, Therkildsen, E, Chiaburu, W. Standfest, “Optimization of Device Performance Using Semiconductor TCAD Tools”. Silvaco International, Product Description, 1995.

K.E.Kaharudin, F.Salehuddin, A.S.M.Zain, M.N.I.A.Aziz, “Impact of Different Dose, Energy and Tilt Angle in Source/Drain Implantation for Vertical Double Gate PMOS Device”, Journal of Telecommunication, Electronic and Computer Engineering, vol. 8, no. 5, pp. 23-28, 2016.

Downloads

Published

2018-07-05

How to Cite

Salehuddin, F., Roslan, A. F., Zailan, A., Kaharudin, K., Zain, A., A.H., A. M., Hanim, A., Hazura, H., Idris, S., & Mohd Saad, W. H. (2018). Analyze Of Process Parameter Variance In 19nm Wsi2/Tio2 NMOS Device Using 2k-Factorial Design. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 10(2-7), 127–131. Retrieved from https://jtec.utem.edu.my/jtec/article/view/4438

Most read articles by the same author(s)

1 2 3 > >>