Analyze Of Process Parameter Variance In 19nm Wsi2/Tio2 NMOS Device Using 2k-Factorial Design

Authors

  • F. Salehuddin Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka
  • Ameer F. Roslan Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka
  • A.E. Zailan Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka
  • K.E. Kaharudin Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka
  • A.S.M. Zain Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka
  • Afifah Maheran A.H. Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka
  • A.R. Hanim Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka
  • H. Hazura Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka
  • S.K. Idris Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka
  • Wira Hidayat Mohd Saad Micro and Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka

Keywords:

2k-factorial Design, Ion implantation, NMOS Device,

Abstract

This project investigates and analyzes the impact of process parameter variance on the drive current (ION) and leakage current (IOFF) for 19nm WSi2/TiO2 NMOS device using 2k-factorial design. The four process parameter, namely halo implant dose, halo implant energy, source/drain (S/D) implant dose and S/D implant energy will be investigated and adjusted to improve the results. The simulated of the device was performed by using ATHENA module. Meanwhile the electrical characterization of the device was implemented by using ATLAS module. These two modules will be combined with 2kfactorial to aid design and optimize the process parameters. The most effective process parameter with respect ION and IOFF were chosen depending on the percentage of the factor effect on S/N ratio that indicates the relative power of factor to reduce variation. The most dominant or significant factors in S/N Ratio are pocket halo implant dose and S/D implant energy. Meanwhile, the values of ION and IOFF values for 19nm WSi2/SiO2 NMOS device after optimization approaches are 591.38 µA/µm and 2.217 pA/µm respectively. The results obtained are meet the requirement of International Technology Roadmap Semiconductor (ITRS) 2013 prediction.

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Published

2018-07-05

How to Cite

Salehuddin, F., Roslan, A. F., Zailan, A., Kaharudin, K., Zain, A., A.H., A. M., Hanim, A., Hazura, H., Idris, S., & Mohd Saad, W. H. (2018). Analyze Of Process Parameter Variance In 19nm Wsi2/Tio2 NMOS Device Using 2k-Factorial Design. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 10(2-7), 127–131. Retrieved from https://jtec.utem.edu.my/jtec/article/view/4438

Issue

Vol. 10 No. 2-7: Embracing The 4th Industrial Revolution: Innovation in Telecommunication, Electronic & Computer Engineering III

Section

Articles

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