Development Design of Fault-Tolerant Soft-Core Based on Error Correction Code in FPGA

Abstract

This paper presented the development of Faulttolerant soft-core that was implemented based on Error Correction Code (ECC). A simulation of behavioral module was carried out using Xilinx ISE Design Suite Software. The design focuses on Fault-Tolerant Hamming Code, Single-ErrorCorrection Double-Error-Detection (SEC-DED) Code and Triple Modular Redundancy (TMR) code that is synthesizable in the Field of Programmable Gate Array (FPGA) Verilog. The faults have been injected into the Fault-Tolerant module. The experiment results were compared as the error detection and the error recovered simulated as simulation results.