Development Design of Fault-Tolerant Soft-Core Based on Error Correction Code in FPGA

Authors

  • Mohd Hafiz Sulaiman Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka (UTeM), Melaka, Malaysia.
  • Sani Irwan Md Salim Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka (UTeM), Melaka, Malaysia.
  • Masrullizam Mat Ibrahim Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka (UTeM), Melaka, Malaysia.

Keywords:

Fault-Tolerant, ECC, Hamming, SEC-DED, TMR, FPGA,

Abstract

This paper presented the development of Faulttolerant soft-core that was implemented based on Error Correction Code (ECC). A simulation of behavioral module was carried out using Xilinx ISE Design Suite Software. The design focuses on Fault-Tolerant Hamming Code, Single-ErrorCorrection Double-Error-Detection (SEC-DED) Code and Triple Modular Redundancy (TMR) code that is synthesizable in the Field of Programmable Gate Array (FPGA) Verilog. The faults have been injected into the Fault-Tolerant module. The experiment results were compared as the error detection and the error recovered simulated as simulation results.

Downloads

Downloads

Published

2017-06-01

How to Cite

Sulaiman, M. H., Md Salim, S. I., & Mat Ibrahim, M. (2017). Development Design of Fault-Tolerant Soft-Core Based on Error Correction Code in FPGA. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 9(2-4), 161–163. Retrieved from https://jtec.utem.edu.my/jtec/article/view/2380

Issue

Vol. 9 No. 2-4: Circuit and System Advancement in Modern World III

Section

Articles

License

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0)

Most read articles by the same author(s)