Design of Shallow Source/Drain Extension (SDE) Profiles in Improving Short -Channel Effect (SCE) in Nanoscale Devices

Abstract

This paper purposed the design of shallow source/drain extension (SDE) in improving short channel effect (SCE) in nanoscale devices. In order to increase the mobility and the speed of the electronic devices, semiconductor technology researchers face the limitations such as short channel effect in MOSFET device as it is unavoidable in scaling. Thus, the aim of this project is to improve the short-channel effect in nanoscale devices. The design parameter standard structure of MetalOxide-Semiconductor Field-Effect Transistor (MOSFET) were proposed referring to the International Technology Roadmap for Semiconductors (ITRS) 2011 edition and compared the structure with same standard structure of ITRS with modification to the junction depth that becomes more shallow source/drain extension (SDE). Silvaco’s DEVEDIT software is used to design the structure of MOSFET with three different gate lengths, while Silvaco’s ATLAS software is used to simulate the structure for data extraction to obtain the output graph. From the output, it shows that, as the size of MOSFET gate length becomes smaller, the threshold voltages also decrease. In improving the SCE, the value of threshold voltage, Vth, is slightly increases on shallower the source/drain extension (SDE). The value of “ON’’ current (ION) also has been extracted for all designs of MOSFET.