Implementation of Taguchi Method for Lower Drain Induced Barrier Lowering in Vertical Double Gate NMOS Device

Authors

  • K.E. Kaharudin Centre for Telecommunication Research and Innovation, Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka (UTeM), Hang Tuah Jaya, Durian Tunggal, 76100 Melaka.
  • F. Salehuddin Centre for Telecommunication Research and Innovation, Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka (UTeM), Hang Tuah Jaya, Durian Tunggal, 76100 Melaka.
  • A.S.M. Zain Centre for Telecommunication Research and Innovation, Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka (UTeM), Hang Tuah Jaya, Durian Tunggal, 76100 Melaka.
  • M.N.I A. Aziz Centre for Telecommunication Research and Innovation, Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka (UTeM), Hang Tuah Jaya, Durian Tunggal, 76100 Melaka.

Keywords:

ANOVA, DIBL, SNR, Taguchi Method,

Abstract

This paper presents a study in which an attempt has been made to reduce the drain induced barrier lowering (DIBL) in Vertical Double Gate NMOS device by optimizing multiple process parameter using L12 orthogonal array of Taguchi method. The device performance depended on the amount of DIBL effects that were successfully suppressed in the device. The Taguchi method comprised an orthogonal array (OA), main effects, signal-to-noise ratio (SNR) and analysis of variance (ANOVA) which were employed to analyze the effects of multiple process parameters on the DIBL of the device. Analysis of the experimental results revealed that the halo implant tilt angle was the most dominant process parameter which had a major influence on DIBL value with 62% of factor effect on SNR. Meanwhile, the lowest possible DIBL value retrieved after the optimization approach was observed to be 43.97 mV/V.

References

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Published

2016-07-01

How to Cite

Kaharudin, K., Salehuddin, F., Zain, A., & A. Aziz, M. (2016). Implementation of Taguchi Method for Lower Drain Induced Barrier Lowering in Vertical Double Gate NMOS Device. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 8(4), 11–16. Retrieved from https://jtec.utem.edu.my/jtec/article/view/1196

Issue

Vol. 8 No. 4: Pioneering Future Innovation Through Green Technology II

Section

Articles

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