Implementation of Taguchi Method for Lower Drain Induced Barrier Lowering in Vertical Double Gate NMOS Device

Authors

  • K.E. Kaharudin Centre for Telecommunication Research and Innovation, Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka (UTeM), Hang Tuah Jaya, Durian Tunggal, 76100 Melaka.
  • F. Salehuddin Centre for Telecommunication Research and Innovation, Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka (UTeM), Hang Tuah Jaya, Durian Tunggal, 76100 Melaka.
  • A.S.M. Zain Centre for Telecommunication Research and Innovation, Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka (UTeM), Hang Tuah Jaya, Durian Tunggal, 76100 Melaka.
  • M.N.I A. Aziz Centre for Telecommunication Research and Innovation, Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka (UTeM), Hang Tuah Jaya, Durian Tunggal, 76100 Melaka.

Keywords:

ANOVA, DIBL, SNR, Taguchi Method,

Abstract

This paper presents a study in which an attempt has been made to reduce the drain induced barrier lowering (DIBL) in Vertical Double Gate NMOS device by optimizing multiple process parameter using L12 orthogonal array of Taguchi method. The device performance depended on the amount of DIBL effects that were successfully suppressed in the device. The Taguchi method comprised an orthogonal array (OA), main effects, signal-to-noise ratio (SNR) and analysis of variance (ANOVA) which were employed to analyze the effects of multiple process parameters on the DIBL of the device. Analysis of the experimental results revealed that the halo implant tilt angle was the most dominant process parameter which had a major influence on DIBL value with 62% of factor effect on SNR. Meanwhile, the lowest possible DIBL value retrieved after the optimization approach was observed to be 43.97 mV/V.

References

M. A. Karim, S.V., Yogesh Singh Chauhan, Darsen Lu, Ali Niknejad and Chenming Hu. 2011. Drain Induced Barrier Lowering (DIBL) Effect on the Intrinsic Capacitances of Nano-Scale MOSFETs. in Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo.

Sudhansu Kumar Pati, H.P., Godwin Raj, Chandan Kumar Sarkar. 2013.Comparison study of Drain Current, Subthreshold Swing and DIBL of III-V Heterostructure and Silicon Double Gate MOSFET. Journal of Electronics & Communication Technology, 4(1): 33-35.

F. Salehuddin, K. Kaharudin, A. S. M. Zain, A. K. Mat Yamin, I. Ahmad. 2014. Analysis of process parameter effect on DIBL in nchannel MOSFET device using L27 orthogonal array. International Conferences on Fundamental and Applied Sciences, AIP Conf. Proc.322: 322-328.

Afifah Maheran, A.H., Menon, P. S., I. Ahmad, S. Shaari. 2014.Optimisation of Process Parameters for Lower Leakage Current in 22 nm n-type MOSFET Device using Taguchi Method. Jurnal Teknologi,68(4): 1-5.

F. Salehuddin, I. Ahmad, F. A. Hamid, A. Zaharim, U. Hashim, P. R. Apte. 2011. Optimization of input process parameters variation on threshold voltage in 45 nm NMOS device. International Journal of the Physical Sciences. 6(30): 7026-7034.

H. Abdullah, J. H. Jurait., A. Lennie, Z. M. Nopiah, I. Ahmad. 2009.Simulation of Fabrication Process VDMOSFET Transistor Using Silvaco Software. European Journal of Scientific Research. 29(4): 461-470.

K. E. Kaharudin, A. H. Hamidon., F. Salehuddin. 2014. Implementation of Taguchi Modeling for Higher Drive Current (ION) in Vertical DGMOSFET Device. Journal of Telecommunication, Electronic and Computer Engineering, 6(2): 11-18.

S. Kamaruddin, Z. A. Khan, S. H. Foong. 2010. Application of Taguchi Method in the Optimization of Injection Moulding Parameters for Manufacturing Products from Plastic Blend. International Journal of Engineering and Technology, 14(6): 152-166.

A. Asghar, A. A. Abdul Rahman, W. M. A. Wan Daud. 2014. A Comparison of Central Composite Design and TaguchiMethod for Optimizing Fenton Process. The Scientific World Journal, 2014: 1-14.

F. Salehuddin, I. Ahmad., F. A. Hamid, A. Zaharim. 2011. Application of Taguchi Method in Optimization of Gate Oxide and Silicide Thickness for 45nm NMOS Device. International Journal of Engineering & Technology, 9(10): 94-98.

H. A. Elgomati, I.A., F. Salehuddin, F. A. Hamid, A. Zaharim, B. Y. Majlis, P. R. Apte. 2011. Optimal Solution in Producing 32nm CMOS Technology Transistor with Desired Leakage Current. International Journal Semiconductor Physics Quantum Electron Optoelectron, 14(2): 145-151.

K. E. Kaharudin, A. H. Hamidon., F. Salehuddin. 2014. Impact of Height of Silicon Pillar on Vertical DG-MOSFET Device. International Journal of Computer, Information, Systems and Control Engineering,8(4): 576-580.

F. Salehuddin, I. Ahmad., F. A. Hamid, A. Zaharim. 2011. Application of Taguchi Method in Optimization of Gate Oxide and Silicide Thickness for 45nm NMOS Device. International Journal

of Engineering & Technology, 9(10): 94-98.

Phadke, M.S. 2001. Quality Engineering Using Robust Design. Pearson Education, Inc. and Dorling Kindersley Publishing, Inc.

M. Nalbant, H. Gokkaya., G. Sur. 2007. Application of Taguchi Method in Optimization of Cutting Parameters for Surface Roughness Tu rning.International Journal Materials and Design, 28: 1379-1385.

I. Saad, R. Ismail. 2008. Self-aligned vertical double-gate MOSFET (VDGM) with the oblique rotating ion implantation (ORI) method .Microelectronics Journal, 39(12): 1538-1541.

J. Rahul, S. Yadav, V. Bohat. 2014. Effects of Metal Gate Electrode and HfO2 in Junction less Vertical Double Gate MOSFET. International Journal of Scientific Engineering and Technology. 674(3): 671-674.

Downloads

Published

2016-07-01

How to Cite

Kaharudin, K., Salehuddin, F., Zain, A., & A. Aziz, M. (2016). Implementation of Taguchi Method for Lower Drain Induced Barrier Lowering in Vertical Double Gate NMOS Device. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 8(4), 11–16. Retrieved from https://jtec.utem.edu.my/jtec/article/view/1196

Most read articles by the same author(s)

1 2 > >>