Challenges for 0.13µm Generation Shallow Trench Isolation on 0.18µm Equipment Platform

Abstract

In order to stay competitive, the industry needs to process lower technology node from CMOS 0.18µm to 0.13µm on similar equipment platform. This will avoid at least USD 50 million CAPEX. The adaptation of lower geometry technology in older equipment platform is very challenging as similar approach can lead to yield loss to the wafer, hence not meeting the business requirement. This paper presents an integration engineering approach to enable process capability that meets circuit probe sort yield. The experiment will use series of 200mm wafer process equipment, KLA-Tencor 2367UV/Visible bright-field inspection system and data Power yield management systems to understand the root cause and implement new solution. The study found that the process recipe for shallow trench isolation (STI) deposition void that causes poly stringer defect is the stoppage for 0.13µm qualification on the 0.18µm equipment. Further defect formation will be discussed also. This paper reveals various process optimizations and re-designs of the STI layout with Optical Proximity Correction (OPC) tagging approaches that have been evaluated to eliminate the defects. The results from this paper demonstrate that a successful improvement method is able to qualify the CMOS 0.18µm to 0.13µm on similar equipment platform with outstanding sort yield