Challenges for 0.13µm Generation Shallow Trench Isolation on 0.18µm Equipment Platform

Authors

  • Thung Beng Joo Silterra Malaysia Sdn. Bhd. Kulim Hi-Tech Park, 09000 Kulim, Kedah, Malaysia
  • Kader Ibrahim Silterra Malaysia Sdn. Bhd. Kulim Hi-Tech Park, 09000 Kulim, Kedah, Malaysia
  • Nurulfajar Abd Manap Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka (UTeM), Malaysia
  • Fauziyah Salehuddin Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka (UTeM), Malaysia

Keywords:

Shallow Trench Isolation (STI), Optical Proximity Correction (OPC), Complementary Metal-oxide Semiconductor (CMOS), Semiconductor Fabrication,

Abstract

In order to stay competitive, the industry needs to process lower technology node from CMOS 0.18µm to 0.13µm on similar equipment platform. This will avoid at least USD 50 million CAPEX. The adaptation of lower geometry technology in older equipment platform is very challenging as similar approach can lead to yield loss to the wafer, hence not meeting the business requirement. This paper presents an integration engineering approach to enable process capability that meets circuit probe sort yield. The experiment will use series of 200mm wafer process equipment, KLA-Tencor 2367UV/Visible bright-field inspection system and data Power yield management systems to understand the root cause and implement new solution. The study found that the process recipe for shallow trench isolation (STI) deposition void that causes poly stringer defect is the stoppage for 0.13µm qualification on the 0.18µm equipment. Further defect formation will be discussed also. This paper reveals various process optimizations and re-designs of the STI layout with Optical Proximity Correction (OPC) tagging approaches that have been evaluated to eliminate the defects. The results from this paper demonstrate that a successful improvement method is able to qualify the CMOS 0.18µm to 0.13µm on similar equipment platform with outstanding sort yield

Author Biography

Thung Beng Joo, Silterra Malaysia Sdn. Bhd. Kulim Hi-Tech Park, 09000 Kulim, Kedah, Malaysia

Thung Beng Joo is Fab Integration Director in SilTerra Malaysia Sdn. Bhd. He earned Master of Science (MSc) in microelectronics and information system from Liverpool John Moores University, United Kingdom. He has various working experience in multi-national companies such as Komag Corp., Intel Corp., Showa Aluminum Corp prior to join SilTrra Malaysia. He leads Fab Integration, Yield Enhancement, Data Mining, Electrical Test and Defect Reduction modules.

References

K. Ibrahim, M. A. Chik, and U. Hashim, “Horrendous Capacity Cost of Semiconductor Wafer Manufacturing,” in International Conference of Semiconductor Electronics 2014 (IEEE-ICSE2014 Proc. 2014, 2014, pp. 345–348.

M. A. Chik, K. Ibrahim, M. H. Saidin, F. Yusof, G. Devandran, U. Hashim, and J. K. Setar, “Development of Capacity Indices for Semiconductor Fabrication,” in International conference of semiconductor Electronics, 2012, pp. 684–688.

M. A. Chik, V. C. Yung, P. Balakrishna, U. Hashim, I. Ahmad, and B. Mohamad, “A study for Optimum Productivity Yield in 0.16 µ m mixed of Wafer Fabrication Facility,” in international conference of Semiconductor Electronics 2010, 2010, pp. 444–447

M. A. Chik, V. C. Yung, P. Balakrishna, U. Hashim, I. Ahmad, and B. Mohamad, “A study for Optimum Productivity Yield in 0.16 µ m mixed of Wafer Fabrication Facility,” in international conference of Semiconductor Electronics 2010, 2010, pp. 444–447

I. A. N. Gohl, H. S. Chua, T. L. Neo, Y. Y. Soh, I. C. Chiang, E. W. Tan, G. Y. Tey, K. J. How, K. F. Wong, and S. W. Yeoh, “An integrated engineering approach to improve wafer edge vield,” IEEE, vol. 3, no. 65, pp. 5–8, 2001.

T. Carey, M. Lorenz, and J. Dougan, “Yield Improvement through Implementation of Edge Scrub at Post Oxide Dielectric,” IEEE Commun. Surv. Tutorials, pp. 3–6, 2003.

O. T. Drive, “Yield Analysis Methodology For Low Defectivity Wafer Fabs Yield Components for Low Defectivity,” pp. 65–69, 2000.

S. and N. Kawashima, “Implementation Requirements for Edge Exclusion Area Reduction for Maximized Output of Chips from a 200mm wafer,” pp. 98–101, Jan. 1992.

K. J. Kuhn, D. Mei, I. Post, and J. Neirynck, “Scaling challenges for 0.13um generation shallow trench isolation,” IEEE pp. 2–5, 2001.

B. Delahaye, J. L. Baltzinger, L. Denis, S. Chantepie, P. Costaganna, G. Richou, S. Lariviere, F. Aonzo, S. Delabriere, F. Poli, C. Bru, J. B. Meyniel, F. Allais, V. Dureuil, P. Raffin, and E. Rondey, “Edge and extreme edge wafer manufacturing on 200 mm wafer: Methodology, yield challenges, cost effective solutions, limitations,” 2009 IEEE/SEMI Adv. Semicond. Manuf. Conf., pp. 100–105, May 2009.

M.Nandakumar, A.Chatterjee, S.Sridhar, K.Joyner, M.Rodder and I.-C.Chen, “Shallow Trench Isolation for advanced ULSI CMOS Technologies,” IEDM 98-133

H. P. Mungekar and Y. S. Lee, “High density plasma chemical vapor deposition gap-fill mechanisms,” J. Vac. Sci. Technol. B Microelectron. Nanom. Struct., vol. 24, no. 2, pp. L11–L15, 2006.

S.V.Nguyen, G.Freeman, D.Dobuzinsky, K.Kellerher, R.Nowak, T.Sahin, and D.Witty, “Characterization of High Density Plasma Deposition Silicon Oxide Dielectric for 0.25µm ULSI,” Proceedings of the 12th International VLSI Multilevel Interconnection Conference, 1995, pp. 69-75

Y.Wang, I.Valle, S.Ritterbush, J.Qiao, C.Chan, S.Li, P.Narwankar, J.Hamila, A.Collins, T.Shahin, C.Leung, and F.Moghaddam, “Process Window Characterization of UTIMA HDP-CVD USG Films”, Proceedings of the Thirds International Dielectrics for USLI Multilevel Interconnection Conference, 1997, pp. 405-408.

F.Lee, P.Wang, R.Ceton, R.Goodner, and M.Chan, “Yield Enhancement Strategies for Start-up of a High Volume 8-inch Wafer Fab”, Proceedings of IEEE/SEMI Advenced Semiconductor Manufacturing Conference, pp267-70, 1995.

J. Indahwan, Z. G. Song, T. Tun, C. K. Oh, and K. F. Lo, “Failure Analysis on Wafer Edge Issue in 0.13um Technology,” ICSE2004 vol. 00, no. c, pp. 268–270, 2004.

R. M. Dumlao, K. P. Ulland, M. S. A. C. Marcos, and D. Beasterfield, “Wafer sort yield improvement by localizing and applying optical proximity correction on a metal bridging issue,” 2010 34th IEEE/CPMT Int. Electron. Manuf. Technol. Symp., pp. 1–4, Nov. 2010.

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Published

2016-08-01

How to Cite

Beng Joo, T., Ibrahim, K., Abd Manap, N., & Salehuddin, F. (2016). Challenges for 0.13µm Generation Shallow Trench Isolation on 0.18µm Equipment Platform. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 8(5), 15–21. Retrieved from https://jtec.utem.edu.my/jtec/article/view/697

Issue

Vol. 8 No. 5: May - August 2016

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Articles

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