An Optimal Mobile Hardware Design for Inter Motion Estimation in HEVC

Authors

  • Toan Nguyen School of Electronics and Telecommunications, Hanoi University of Science and Technology, Hanoi, Vietnam.
  • Cuong Pham School of Electronics and Telecommunications, Hanoi University of Science and Technology, Hanoi, Vietnam.
  • Canh Dinh School of Electronics and Telecommunications, Hanoi University of Science and Technology, Hanoi, Vietnam.
  • Phong Nguyen School of Electronics and Telecommunications, Hanoi University of Science and Technology, Hanoi, Vietnam.
  • Thang Nguyen School of Electronics and Telecommunications, Hanoi University of Science and Technology, Hanoi, Vietnam.

Keywords:

H.265/HEVC, H.264/MPEG-4, FPGA, Motion Estimation (ME), Inter Motion Estimation (IME),

Abstract

This paper presents a hardware design for the Integer Motion Estimation (IME) compatible with the High Efficiency Video Coding (HEVC) standard. The hardware designed was targeted to meet 1080p@30fps real-time video coding. The architectures were described in Verilog HDL and synthesis on Xilinx Virtex VI. The proposed techniques significantly reduce the area and energy consumption of the proposed hardware on FPGA.

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Published

2016-09-01

How to Cite

Nguyen, T., Pham, C., Dinh, C., Nguyen, P., & Nguyen, T. (2016). An Optimal Mobile Hardware Design for Inter Motion Estimation in HEVC. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 8(6), 27–31. Retrieved from https://jtec.utem.edu.my/jtec/article/view/1240

Issue

Vol. 8 No. 6: Emerging Technologies in Communication and Computer Engineering for Smart City Applications II

Section

Articles

License

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0)