An Optimal Mobile Hardware Design for Inter Motion Estimation in HEVC
Keywords:H.265/HEVC, H.264/MPEG-4, FPGA, Motion Estimation (ME), Inter Motion Estimation (IME),
AbstractThis paper presents a hardware design for the Integer Motion Estimation (IME) compatible with the High Efficiency Video Coding (HEVC) standard. The hardware designed was targeted to meet 1080p@30fps real-time video coding. The architectures were described in Verilog HDL and synthesis on Xilinx Virtex VI. The proposed techniques significantly reduce the area and energy consumption of the proposed hardware on FPGA.
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