A Novel Parallel Hardware Architecture for Inter Motion Estimation in HEVC

Authors

  • Canh Dinh School of Electronics and Telecommunications, Hanoi University of Science and Technology, Hanoi, Vietnam.
  • Toan Nguyen School of Electronics and Telecommunications, Hanoi University of Science and Technology, Hanoi, Vietnam.
  • Cuong Pham School of Electronics and Telecommunications, Hanoi University of Science and Technology, Hanoi, Vietnam.
  • Phong Nguyen School of Electronics and Telecommunications, Hanoi University of Science and Technology, Hanoi, Vietnam.
  • Duc Duong School of Electronics and Telecommunications, Hanoi University of Science and Technology, Hanoi, Vietnam.
  • Ha Phung School of Electronics and Telecommunications, Hanoi University of Science and Technology, Hanoi, Vietnam.
  • Tien Pham School of Electronics and Telecommunications, Hanoi University of Science and Technology, Hanoi, Vietnam.
  • Thang Nguyen School of Electronics and Telecommunications, Hanoi University of Science and Technology, Hanoi, Vietnam.

Keywords:

H.265/HEVC, H.264/MPEG-4, FPGA, Motion Estimation (ME), Inter Motion Estimation (IME),

Abstract

High Efficiency Video Coding (HEVC) standard, generated by ITU, can provide compression ratio twice more than current H.264/ MPEG-4. To date, only a few hardware have been implementated for Integer Motion Estimation (IME) to date. In this paper, a parallel hardware architecture for IME in HEVC encoder is proposed. This design uses Rot-WDiamond (RWD) algorithm to reduce computational load and parallelism to improve processing speed. Therefore, this design can reach 4K (4096×2160) video in real time at 60 frames per second (fps) and achieve the frequency of 125MHz.

References

Sullivan, Gary J., Jens-Rainer Ohm, Woo-Jin Han, and Thomas Wiegand. "Overview of the high efficiency video coding (HEVC) standard." IEEE Transactions on circuits and systems for video technology 22, no. 12, pp. 1649-1668, 2012.

Zhao, Z. and Liang, P., "A statistical analysis of h. 264/avc fme mode reduction." IEEE transactions on circuits and systems for video technology 21, no. 1, pp. 53-61, 2011.

Vanne, J., Viitanen, M., Hamalainen, T.D. and Hallapuro, A.,

“Comparative Rate-Distortion-Complexity Analysis of HEVC and

AVC Video Codecs” IEEE Transactions on Circuits and Systems for

Video Technology 22, no. 12, pp. 1885-1898, 2012.

Nguyen, P., Tran, H., Nguyen, H., Nguyen, X.N., Vo, C., Nguyen, B., Ngo, V.D. and Nguyen, V.T. “Asymmetric diamond search pattern for motion estimation in HEVC,” In Communications and Electronics (ICCE), 2014 IEEE Fifth International Conference on, pp. 434-439, 2014.

Ye, X., Ding, D. and Yu, L., "A hardware-oriented IME algorithm and its implementation for HEVC," In Visual Communications and Image Processing Conference, 2014 IEEE, pp. 205-208, 2014.

Yuan, X., Jinsong, L., Liwei, G., Zhi, Z., and Teng, R. K. “A high performance VLSI architecture for integer motion estimation in HEVC”. In ASIC (ASICON), 2013 IEEE 10th International

Conference on, pp. 1-4, 2013.

Byun, J., Jung, Y., and Kim, J. “Design of integer motion estimator of HEVC for asymmetric motion-partitioning mode and 4K-UHD”. Electronics Letters, vol. 49, no. 18, pp. 1142-1143, 2013.

Vidyalekshmi, V. G., Yagain, D., and Rao, G..”Motion estimation block for HEVC encoder on FPGA”. In Recent Advances and Innovations in Engineering (ICRAIE), pp. 1-5, 2014.

Downloads

Published

2017-03-15

How to Cite

Dinh, C., Nguyen, T., Pham, C., Nguyen, P., Duong, D., Phung, H., Pham, T., & Nguyen, T. (2017). A Novel Parallel Hardware Architecture for Inter Motion Estimation in HEVC. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 9(1-3), 83–88. Retrieved from https://jtec.utem.edu.my/jtec/article/view/1749