Electrical Tests for Capacitive Open Defects in Assembled PCBs

Authors

  • Fara Ashikin Alia Faculty of Engineering Technology, Universiti Teknikal Malaysia Melaka, Malaysia.
  • Akihiro Odoriba Graduate School of Technology and Science, Tokushima University, Japan.
  • Masaki Hashizume Graduate School of Technology and Science, Tokushima University, Japan.
  • Hiroyuki Yotsuyanagi Graduate School of Technology and Science, Tokushima University, Japan.
  • Shyue-Kung Lu National Taiwan University of Science and Technology, Taiwan.

Keywords:

Design for Testability, Electrical Test, Open Defects,

Abstract

Nowadays, Ball Grid Array (BGA) becomes a major packaging type due to its high bulk for input/output (I/O) pins. However, there are defects such as voids and cracks occurring between a BGA IC and a PCB which may result in an electrical failure in the circuit. This paper presents electrical tests for capacitive open defects occurring at an interconnection between an IC and a PCB. Feasibility of the electrical test with the test circuit is evaluated by SPICE simulation and experiments. Capacitive open defects occurring at interconnects are detected by the test method. Both simulation and experimental results showed that capacitive open defects generating no logical errors can be detected by the test method at a test speed of 1kHz and 1MHz.

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Published

2017-10-15

How to Cite

Alia, F. A., Odoriba, A., Hashizume, M., Yotsuyanagi, H., & Lu, S.-K. (2017). Electrical Tests for Capacitive Open Defects in Assembled PCBs. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 9(3-2), 49–52. Retrieved from https://jtec.utem.edu.my/jtec/article/view/2812