Electrical Test of Resistive and Capacitive Open Defects at Data Bus in 3D Memory IC

Authors

  • Masaki Hashizume Tokushima University, Tokushima, Japan.
  • Yudai Shiraishi Tokushima University, Tokushima, Japan.
  • Hiroyuki Yotsuyanagi Tokushima University, Tokushima, Japan.
  • Hiroshi Yokoyama Akita University, Akita, Japan.
  • Tetsuo Tada Tokushima Bunri University, Shido, Kagawa, Japan.
  • Shyue-Kung Lu National Taiwan Univ. of Science and Technology, Taipei, Taiwan.

Keywords:

3D memory IC, Data bus, Open defect, Supply current test.

Abstract

We propose an electrical test method of resistive and capacitive open defects occurring at data bus lines between dies, and between dies and I/O pins in 3D memory ICs. The test method is based on supply current of an IC. The number of test vectors for a 3D memory IC made of ND memory dies in the test method is 10∙ND and small. Also, defective interconnects are located by the test method. Feasibility of the tests is examined by some experiments for a circuit made of an SRAM IC on a printed circuit board. The experimental results show that capacitive open defects and resistive open ones whose resistance values are greater than 200Ω can be detected by the test method.

References

Pavlidis, V. F., and E. G. Friedman. 2009. Three-dimensional Integrated Circuit Design. USA: Morgan Kaufman.

Lee, H-H. S., and K. Chakrabarty. 2009. Test Challenges for 3D Integrated Circuits. IEEE Design & Test of Computers. 26(5):26-35.

Marinissen, E. J., and Y. Zorian. 2009. Testing 3D Chips Containing Through-Silicon Vias. IEEE International Test 2009. Texas, USA. 1-6 November 2009. 1-11. Conference (ITC),

Noia, B., K. Chakrabarty, and E. J. Marinissen. 2010. Optimization Methods for Post-Bond Die-Internal/External Testing in 3D Stacked ICs. IEEE International Test Conference (ITC), 2010. Texas, USA. 31 October - 5 November 2010. 1-9.

CWhuo.u ,2 C0.1 0W. .,A J. FT. eLsti , JI.n Jte. gCrahteino,n DM. Met.h Kodwoaloi,g Yy . Ffo. rC h3oDu , aInntde gCr.a tWed. Circuits. The 19th IEEE Asian Test Symposium (ATS), 2010. Shanghai, China, 1-4 December 2010. 377-382.

Huang, Y. J., J. F. Li, J. J. Chen, D. M. Kwai, Y. F. Chou, and C. W. TWSuV. s2 i0n1 31D. A IC Bs.u 2il9t-thIn I ESEeElf -VTeLsSt I STcehsetm Sey mfopro sthiuem P (oVstT-BS)o, n2d0 1T1e.s Ct Aof, USA. 1-5 May 2011. 20-25.

Aoyagi, M., F. Imura, S. Nemoto, N. Watanabe, F. Kato, K. Kikuchi, H. Nakagawa, M. Hasimoto, H. Uchida and Y. Matsumoto. 2012. Wide Bus Chip-toChip Interconnection Technology Using Fine Pitch SByummppo sJiuomin tJ apAarnr a(yIC SfoJ)r, 230D12 . LKSyIo toC,h Jiapp anS.t a1c0k-i1n2g .D eIcEeEmEb erC 2P0M12T. 183-186.

Kandalaft, N., R. Rashidzadeh, and M. Ahmadi. 2013. Testing 3-D IC Through-Silicon-Vias (TSVs) by Direct Probing. IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems. 32(4):

5F3k8ih-5, 4Y6.., P. Vivet, G. D. Natale, M-L. Flottes, and B. Rouzeyre. 2013. A 3D IC BIST for pre-bond test of TSVs using Ring Oscillators. IEEE 11th International New Circuits and Systems Conference (NEWCAS), 2013. Paris, France. 16-19 June 2013. 1-4.

Taouil, M., M. Masadeh, S. Hamdioui and E. J. Marinisen. 2014. Internconnect Test for 3D Stacked Memory-on-Logic. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014. Dresden, Germany. 24-28 March 2014. 1-6.

CYhea. k2u0r1a4b.a Trteys,t Kan.,d M D. eAsiggrna-wfoarl-,T Se.s Dtaebuiltistcyh S, oBlu. tNioonias ,f oRr. 3WDa nIngt,e agnradt eFd. Circuits. IPSJ Transaction on System LSI Design Methodology. 7:56- 73.

Gambino, J. P., S. A. Adderly, and J. U. Knickerbocker. 2015. An Overview of Through-Silicon-Via Technology and Manufacturing

CKhiraihllaetnag, esT.. ,M Ji.c rGoeolelzc,t roMn.i cW Enogrdineemearinn,g .P 1. 3B5:a7t3ra-,1 0G6.. W. Maier, N. Robson, T. L. Graves-abe, D. Berger, and S. S. Lyer. 2016. Three- Dimensional Dynamic Random Access Memories Using Through- Silicon-Vias. IEEE Journal on Emerging and Selected Topics in

CCihrecnu,i tPs. a Ynd., SCy. sWtem. Ws. u6,( 3an):d3 7D3.- M38.4 K. wai. 2009. On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification. The 18st IEEE Asian Test Symposium (ATS) 2009. Taichung, Taiwan. 23-26 November 2009. 450-455.

You, J. W., S. Y. Huang, D. M. Kwai, Y. F. Chou, and C. W. Wu. 2A0n1a0ly. sPise.r foTrhmea n1c9et hC hIaErEacEt erAizsaitaino n Toef sTt SSVy minp o3sDiu ImC v(iAaT SSe)n, si2ti0v1it0y. Shanghai, China. 1-4 December 2010. 389-394.

Konishi, T., H. Yotsuyanagi, and M. Hashizume. 2012. Supply Current Testing of Open Defects at Interconnects in 3D ICs with IEEE 1149.1 Architecture. IEEE International Conference on 3D FSeybstreumar yI n2t0e1g2r.a t8i-o2n- 1(-38D-2I-C6.) , 2011. Osaka, Japan. 31 January – 2

Konishi, T., H. Yotsuyanagi, and M. Hashizume. 2012. Electrical Test Method for Interconnect Open Defects in 3D ICs. Transaction of the Japan Institute of Electronics Packaging. 5(1):26-33.

Konishi, T., H. Yotsuyanagi, and M. Hashizume. 2012. A Built-in Test Circuit for Supply Current Testing of Open Defects at Interconnects in 3D ICs. 4th Electronics System-Integration Technology Conference (ESTC), 2012. Amsterdam, Netherlands. 17-

2H0a sSheipztuemmeb, erM 2.0, 1T2.. PKAo2n1is.1h_i,1 -aPnAd 2H1..1 _Y6o. t suyanagi. 2013. Electrical Testable Design for Open Defects at Logic Signal Lines between Dies in 3D ICs. IEICE Transaction on Electronics. J96-C(11):361-370. (in Japanese).

Suenaga, S., M. Hashizume, H. Yotsuyanagi, S. K. Lu, and Z. Roth. 2013. DFT for Supply Current Testing to Detect Open Defects at Interconnects in 3D ICs. IEEE Electrical Design of Advanced 1P5ac Dkaegceinmgb &er 2S0y1st3e.m 6s0 -S6y3m. posium (EDAPS), 2013. Nara, Japan. 12-

Hashizume, M., S. Umezu, H. Yotsuyanagi, and S. K. Lu. 2014. A Built-in Supply Current Test Circuit for Electrical Interconnect Tests of 3D ICs. IEEE International Conference on 3D System Integration (3DIC), 2014. Cork, Ireland. 1-3 December 2014. O7-1-O7-6.

Yotsuyanagi, H., A. Fujiwara, and M. Hashizume. 2015. On TSV Array Defect Detection Method Using Two Ring-oscillators Considering Signal Transitions at Adjacent TSVs. IEEE International 3C1o nAfuergeunsct e– o2n S 3epDt eSmybseter m20 I1n5t.e gTrSa8ti.o2n4 .1(3-TDSIC8.)2, 42.40.1 5. Sendai, Japan.

Nanbara, K., A. Odoriba, M. Hashizume, H. Yotsuyanagi and S. K. Lu. 2015. Electrical Interconnect Test of 3D ICs Made of Dies without ESD Protection Circuits with a Built-in Test Circuit. IEEE International Conference on 3D System Integration (3DIC), 2015.

SOednodraibi,a J, aApa.,n .S 3. 1U Amuegzuus,t –M 2. SHeapsthemizubmere 2, 0H15. . YToSt8su.2y2a.n1a-TgiS, 8A.2.2 .A5.. B. Fara, and S. K. Lu. 2015. A Testable Design for Electrical Interconnect Tests of 3D ICs. 2015 International Conference on Electronics Packaging and iMAPS All Asia Conference 2015. Kyoto, Japan. 14-17 April 2015. 718-722.

Hashizume, M., M. Akutagawa, S. K. Lu, and H. Yotsuyanagi. 2013. Electrical Test Method of Open Defects at Bi-directional Interconnects in 3D ICs. 2013 International Conference on 1E3le-c1t8r.o nics Packaging (ICEP) 2013. Osaka, Japan. 10-12 April 2013.

Shiraishi, Y., M. Hashizume, H. Yotsuyanagi, T. Tada, and S. K. Lu. 2014. Electrical Test Method of Open Defects at Data Buses in 3D SRAM IC. 2014 International Conference on Electronics Packaging (ICEP) 2014. Toyama, Japan. 23-25 April 2014. 235-238.

Downloads

Published

2017-10-15

How to Cite

Hashizume, M., Shiraishi, Y., Yotsuyanagi, H., Yokoyama, H., Tada, T., & Lu, S.-K. (2017). Electrical Test of Resistive and Capacitive Open Defects at Data Bus in 3D Memory IC. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 9(3-2), 39–42. Retrieved from https://jtec.utem.edu.my/jtec/article/view/2810

Issue

Vol. 9 No. 3-2: EMPOWERING SCIENCE, ENGINEERING AND TECHNOLOGY TOWARDS GLOBAL MANUFACTURING SUSTAINABILITY

Section

Articles

License

TRANSFER OF COPYRIGHT AGREEMENT

The manuscript is herewith submitted for publication in the Journal of Telecommunication, Electronic and Computer Engineering (JTEC). It has not been published before, and it is not under consideration for publication in any other journals. It contains no material that is scandalous, obscene, libelous or otherwise contrary to law. When the manuscript is accepted for publication, I, as the author, hereby agree to transfer to JTEC, all rights including those pertaining to electronic forms and transmissions, under existing copyright laws, except for the following, which the author(s) specifically retain(s):

  1. All proprietary right other than copyright, such as patent rights
  2. The right to make further copies of all or part of the published article for my use in classroom teaching
  3. The right to reuse all or part of this manuscript in a compilation of my own works or in a textbook of which I am the author; and
  4. The right to make copies of the published work for internal distribution within the institution that employs me

I agree that copies made under these circumstances will continue to carry the copyright notice that appears in the original published work. I agree to inform my co-authors, if any, of the above terms. I certify that I have obtained written permission for the use of text, tables, and/or illustrations from any copyrighted source(s), and I agree to supply such written permission(s) to JTEC upon request.