Electrical Test of Resistive and Capacitive Open Defects at Data Bus in 3D Memory IC

Authors

  • Masaki Hashizume Tokushima University, Tokushima, Japan.
  • Yudai Shiraishi Tokushima University, Tokushima, Japan.
  • Hiroyuki Yotsuyanagi Tokushima University, Tokushima, Japan.
  • Hiroshi Yokoyama Akita University, Akita, Japan.
  • Tetsuo Tada Tokushima Bunri University, Shido, Kagawa, Japan.
  • Shyue-Kung Lu National Taiwan Univ. of Science and Technology, Taipei, Taiwan.

Keywords:

3D memory IC, Data bus, Open defect, Supply current test.

Abstract

We propose an electrical test method of resistive and capacitive open defects occurring at data bus lines between dies, and between dies and I/O pins in 3D memory ICs. The test method is based on supply current of an IC. The number of test vectors for a 3D memory IC made of ND memory dies in the test method is 10∙ND and small. Also, defective interconnects are located by the test method. Feasibility of the tests is examined by some experiments for a circuit made of an SRAM IC on a printed circuit board. The experimental results show that capacitive open defects and resistive open ones whose resistance values are greater than 200Ω can be detected by the test method.

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Published

2017-10-15

How to Cite

Hashizume, M., Shiraishi, Y., Yotsuyanagi, H., Yokoyama, H., Tada, T., & Lu, S.-K. (2017). Electrical Test of Resistive and Capacitive Open Defects at Data Bus in 3D Memory IC. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 9(3-2), 39–42. Retrieved from https://jtec.utem.edu.my/jtec/article/view/2810

Issue

Vol. 9 No. 3-2: EMPOWERING SCIENCE, ENGINEERING AND TECHNOLOGY TOWARDS GLOBAL MANUFACTURING SUSTAINABILITY

Section

Articles

License

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0)