High Gain of 3.1-5.1 GHz CMOS Power Amplifier for Direct Sequence Ultra-Wideband Application

Authors

  • R. Sapawi Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Malaysia Sarawak, 94300, Kota Samarahan, Sarawak, Malaysia.
  • A.N. Asyraf Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Malaysia Sarawak, 94300, Kota Samarahan, Sarawak, Malaysia.
  • D. H. A. Mohamad Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Malaysia Sarawak, 94300, Kota Samarahan, Sarawak, Malaysia.
  • S.K. Sahari Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Malaysia Sarawak, 94300, Kota Samarahan, Sarawak, Malaysia.
  • S.M.W. Masra Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Malaysia Sarawak, 94300, Kota Samarahan, Sarawak, Malaysia.
  • K. Kipli Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Malaysia Sarawak, 94300, Kota Samarahan, Sarawak, Malaysia.
  • N. Julai Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Malaysia Sarawak, 94300, Kota Samarahan, Sarawak, Malaysia.
  • N. Junaidi Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Malaysia Sarawak, 94300, Kota Samarahan, Sarawak, Malaysia.
  • D.N.S.D.A. Salleh Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Malaysia Sarawak, 94300, Kota Samarahan, Sarawak, Malaysia.
  • S.A.Z. Murad School of Microelectronic Engineering, Universiti Malaysia Perlis, Kampus Pauh Putra, Arau, Perlis, Malaysia.

Keywords:

Power Amplifier, Ultra-Wideband, CMOS, Techniques, Performance Criteria

Abstract

This paper presents the design a power amplifier (PA) for direct sequence ultra-wideband applications using 0.13 µm CMOS technology operating in a low band frequency of 3.1 GHz to 5.1 GHz. Current-reused technique is employed at the first stage to increase the gain at the upper end of the desired band. Cascaded common source configuration with shunt peaking inductor at the second stage helps to enhance the wideband frequency while increasing the gain approximately twice the performance. The simulation results specify that high gain of 20.3 dB with ± 0.8 dB flatness, group delay variation of ±121.3 ps, and good input return loss and output return loss is obtained over desired working band. The proposed PA achieves power consumption of 27.3 mW.

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Published

2016-12-01

How to Cite

Sapawi, R., Asyraf, A., Mohamad, D. H. A., Sahari, S., Masra, S., Kipli, K., Julai, N., Junaidi, N., Salleh, D., & Murad, S. (2016). High Gain of 3.1-5.1 GHz CMOS Power Amplifier for Direct Sequence Ultra-Wideband Application. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 8(12), 99–103. Retrieved from https://jtec.utem.edu.my/jtec/article/view/1443

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