Pin Electronic (PE) with Levels Specification Using ATE Tester

Authors

  • Nur Khairunisha Kamel Faculty of Electronic and Computer Technology and Engineering, Universiti Teknikal Malaysia Melaka, 76100 Melaka, Malaysia.
  • Khairuddin Osman Faculty of Electronic and Computer Technology and Engineering, Universiti Teknikal Malaysia Melaka, 76100 Melaka, Malaysia.
  • Norzahirah Zainuddin Kolej Komuniti Selandar, 77500 Melaka, Malaysia.
  • T. Yasuno Graduate School of Advanced Technology and Science, Tokushima University, Japan.

DOI:

https://doi.org/10.54554/jtec.2026.18.01.004

Keywords:

Automated Test Equipment (ATE) , Measurement Precision , Electronic Component , Validation , Simulation and Testing

Abstract

The increasing complexity of electronic components and their stringent performance requirements necessitate precise and reliable testing methodologies. This study explores the development and implementation of a pin electronic system with level specification using Automated Test Equipment (ATE) testers. The purpose of ATE implementation is to drastically reduce human error, increase test throughput, and provide precise, real time data analysis. By utilizing advanced ATE platforms, the study evaluates the accuracy, repeatability, and scalability of the testing process. The proposed approach for the creation of the DTI board is to study the behavior of components that contribute to the levels of VIH, VIHH, and VIL values, thus, influencing the measurement of the PE electronic pins. The results demonstrate significant improvements in measurement precision and test cycle efficiency, offering a robust solution for quality assurance in semiconductor manufacturing. These findings provide valuable insights into optimizing test protocols for high-performance electronic components and pave the way for future advancements in ATE-driven testing methodologies.

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Published

2026-03-31

How to Cite

Kamel, N. K. ., Osman, K., Zainuddin, N., & Yasuno, T. (2026). Pin Electronic (PE) with Levels Specification Using ATE Tester. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 18(1), 29–34. https://doi.org/10.54554/jtec.2026.18.01.004

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