Performance Investigation of Binary Counter with Different Clock Gating Networks


  • Mangal Deep Gupta Department of Electronics and Communication Engineering, MMMUT, Gorakhpur, Uttar Pradesh, India.
  • R. K. Chauhan Department of Electronics and Communication Engineering, MMMUT, Gorakhpur, Uttar Pradesh, India.


Binary Counter, Clock Gating Network (CGN), Delay, FPGA, Layout, Operating Frequency, PDP, Power Dissipation, Slack Time, Verilog HDL,


Three different clock gating network (CGN) have been used in this work to study their impact on the performance of binary counter. Different NMOS and PMOS transistor arrangements were used as CGN network. Its effect on the design of a synchronous binary counter i.e. 4-bit SBC-1T, -2T and -4T was observed to compute some of the essential performance parameters such as delay, slack time, maximum operating frequency, power dissipation, PDP and occupied area. The proposed counter design has been extended for 8 and 16-bit also. For synthesizing (TSMC 180-nm CMOS process) the proposed design, Leonardo Spectrum Tool provided by mentor Graphics has been used. For FPGA synthesis (Spartan-3E) of the proposed design, the ISE design suite provided by Xilinx has been used.


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How to Cite

Deep Gupta, M., & Chauhan, R. K. (2020). Performance Investigation of Binary Counter with Different Clock Gating Networks. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 12(2), 59–67. Retrieved from