A Modified Source Impact Ionisation MOSFET (MS I-MOS) for Low Power and Fast Switching Digital Applications
Keywords:Avalanche, Bipolar Junction Transistor (BJT), DIBL, Impact Ionization, Modified Source, Operating Voltage, Short Channel Effects,
AbstractThis paper presents a two-dimensional (2D) modified source n-p-n impact ionisation MOSFET, called MS IMOS, to suppress the short channel effects and increase the oncurrent (ION) to off-current (IOFF) ratio. The proposed device is an n-p-n I-MOS on silicon on insulator (SOI), upon which a source engineering is performed. The proposed device inherits the characteristics of bipolar I-MOS, with the advantage of reduced floating body effect and the increased ION to IOFF ratio, it exhibits a lower operating voltage than that of earlier I-MOS structures. The reliability issues related to hot carrier injection in the gate oxide has also been addressed effectively in the proposed structure due to lower operating voltage.
International Technology Roadmaps for Semiconductors, ITRS, Albuquerque, NM, USA, 2013.
A. Chaudhry and M. J. Kumar, “Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review,” IEEE Transactions on Device and Materials Reliability, vol. 4, no. 1, pp. 99-109, March 2004.
K. K. Young, “Short-channel effect in fully depleted SOI MOSFETs,” IEEE Transactions on Electron Devices, vol. 36, no. 2, pp. 399-402, Feb 1989.
S. Veeraraghavan and J. G. Fossum, "Short-channel effects in SOI MOSFETs," IEEE Transactions on Electron Devices, vol. 36, no. 3, pp. 522-528, Mar 1989.
B. Bhushan, K. Nayak and V. R. Rao, "DC Compact Model for SOI Tunnel Field-Effect Transistors," IEEE Transactions on Electron Devices, vol. 59, no. 10, pp. 2635-2642, Oct. 2012.
N. Bagga, A. Kumar and S. Dasgupta, "Demonstration of a Novel Two Source Region Tunnel FET," IEEE Transactions on Electron Devices, vol. 64, no. 12, pp. 5256-5262, Dec. 2017.
K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, “Impact ionization MOS (I-MOS)—Part I: Device and circuit simulations,” IEEE Trans. Electronic Devices, vo. 52, no. 1, pp. 69-76, Jan. 2005.
K. Gopalakrishnan, R. Woo, C. Jungemann, P. B. Griffin, and J. D. Plummer, “Impact ionization MOS (I-MOS)—Part II: Experimental results,” IEEE Trans. Electronic Devices, vo. 52, no. 1, pp. 77-84, Jan. 2005.
W. Y. Choi, J. Y. Song, J. D. Lee, Y. J. Park, and B. -G. Park, “100- nm n-/p-channel I-MOS using a novel self-aligned structure,” IEEE Electron Device Lett., vol. 26, no. 4, pp. 261-263, Apr. 2005.
W. Y. Choi, J. Y. Song, B. J. D. Lee, and B. -G. Park, “Effect of source extension junction depth and substrate doping concentration on I-MOS device characteristics,” IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1282-1285, May 2006.
E. -H. Toh, G. H. Wang, L. Chan, G. -Q. Lo, G. Samudra, and Y. -C. Yeo, “Strain and materials engineering for the I-MOS transistor with an elevated impact-ionization region,” IEEE Trans. Electron Devices, vol. 54, no. 10, pp. 2778-2785, Oct. 2007.
C. Onal, R. Woo, H, -Y. S. Koh, P. B. Griffin, and J. D. Pliummer, “A novel depletion I-MOS (DIMOS) device with improved reliability and reduced operating voltage,” IEEE Electron Device Lett., vol. 30, no. 1, pp. 64-67, Jan. 2009.
D. Sarkar, N. Singh, and K. Banerjee, “A novel enhanced electric field impact-ionization MOS transistor,” IEEE Electron Device Lett., vol. 31, no. 11, pp. 1175-1177, Nov. 2010.
S. Ramaswamy, and M. J. Kumar, “Junctionless impact ionization MOS: Proposal and investigation,” IEEE Trans. Electron Devices, vol. 61, no. 12, pp. 4295-4298, Dec. 2014.
M. J. Kumar, M. Maheedhar, and P. P. Varma, “Bipolar I-MOS—An impact ionization MOS with reduced operating voltage using the openbase BJT configuration,” IEEE Trans. Electron Device, vol. 62, no. 12, pp. 4345-4348, Dec. 2015.
A. Lahgree, and M. J. Kumar, “The charge plasma n-p-n impact ionization MOS on FDSOI technology: Proposal and analysis,” IEEE Trans. Electron Devices, vol. 62, no. 12, pp. 4345-4348, Oct. 2016.
V. K. Mishra, and R. K. Chauhan, “Performance analysis of modified source and TDBC based fully-depleted SOI MOSFET for low power digital applications,” Journal of Nanoelectronics, American Scientific Publisher, vol. 12, no. 1, pp. 59-66, 2017.
ATLAS Device simulation software, Silvaco Int., Santa Clara, CA, USA, 2015.
J. P. Colinge, and C. A. Colinge, “Physics of semiconductor devices,” Springer Science & Business Media, 2005, pp. 231-232.
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