High Performance, Fault Tolerance Architecture for Reliable Hybrid Nanometric Memories
Keywords:
Error correction codes, fault tolerance, hardware redundancy, hybrid nanoelectronic memoriesAbstract
Although hybrid nanoelectronic memories (hybrid memories) promise scalability potentials such as ultrascale density and low power consumption, they are expected to suffer from high defect/fault density reducing their reliability. Such defects/faults can impact any part of the memory system including the memory cell array, the encoder and the decoder. This article presents a high-performance, faulttolerant architecture for hybrid memories; it is based on a combination of two techniques: (i) an error correction scheme that tolerates both random and clustered faults in memory cell array and (ii) an on-line masking incorporated into the decoder to tolerate faults in the decoder. Moreover, the decoding process is optimized for area and performance by reversing the decoding sequence. Experimental results show that the proposed architecture realizes a higher performance and competitive reliability level at a comparable overhead as compared with the state-of-the-art. For example, the architecture decodes 5×faster and provides 0.7%better reliability (assuming 10%fault rate) at the cost of similar area overhead (for 1024-bit memory word) as compared to Reed-Solomon codeDownloads
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