Full Custom Rail-to-Rail Self-Calibrating Comparator for Low Voltage Successive Approximation Register Analog-to-Digital Converter

Authors

  • Arnold C. Paglinawan School of Electrical, Electronics and Computer Engineering, Mapúa University, Intramuros 658 Muralla St., Intramuros, Manila 1002, Philippines
  • Febus Reidj Cruz School of Electrical, Electronics and Computer Engineering, Mapúa University, Intramuros 658 Muralla St., Intramuros, Manila 1002, Philippines
  • Charmaine Paglinawan School of Electrical, Electronics and Computer Engineering, Mapúa University, Intramuros 658 Muralla St., Intramuros, Manila 1002, Philippines
  • Mark Oliver Arreza School of Electrical, Electronics and Computer Engineering, Mapúa University, Intramuros 658 Muralla St., Intramuros, Manila 1002, Philippines
  • Lianne Alexa Budomo School of Electrical, Electronics and Computer Engineering, Mapúa University, Intramuros 658 Muralla St., Intramuros, Manila 1002, Philippines
  • Larah Meliss Pinlac School of Electrical, Electronics and Computer Engineering, Mapúa University, Intramuros 658 Muralla St., Intramuros, Manila 1002, Philippines
  • Candy San Juan School of Electrical, Electronics and Computer Engineering, Mapúa University, Intramuros 658 Muralla St., Intramuros, Manila 1002, Philippines
  • Wen Yaw Chung School of Electronics Engineering Chung Yuan Christian University Chungli, Taiwan.
  • Zaliman Sauli School of Microelectronic Engineering, Universiti Malaysia Perlis, Pauh Putra Campus, 02600 Arau, Perlis, Malaysia.

Keywords:

ADC, Rail-to-Rail Comparator, SelfCalibrating Comparator, Novel Rail-to-Rail Self-Calibrating Comparator,

Abstract

The demand for low power consuming devices is increasing, particularly that of wireless sensor networks (WSN). This study aims to address this problem by designing a novel rail-to-rail comparator for SAR ADC integrated with selfcalibration to null offset. In this study, rail-to-rail comparator, self-calibrating comparator, and rail-to-rail self-calibrating comparator are the circuits that will be designed, compared and analyzed. The three circuit designs were realized using the 0.18um CMOS technologyand has undergonePVT variations. The designed comparators all operate with a 1.8 V supply. In comparing and determining which circuit is the best in terms of their response, all the circuits will be compared based on six parameters to be measured thru the use of Simulation Program with Integrated Circuit Emphasis, also known as SPICE. The rail-to-rail comparator design resulted in an ICMR of 700mV. The self-calibratingcomparator design has a prominent value of 78dB for its CMRR. On the other hand, the novel rail-to-rail self-calibrating comparator design has highlighted a 5.15 V/us slew rate, with a power dissipation of only 22.40uW. A layout of the novel rail-to-rail self-calibrating comparator was also implemented which has a power dissipation 25.60uW and a slew rate of 4.16 V/us. It was found that the proposed design’s key features are stable performance over wide temperature ranges from 0°C up to 49°C, high value of slew rate and low power consumption without compromising its function.

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Published

2018-05-30

How to Cite

Paglinawan, A. C., Cruz, F. R., Paglinawan, C., Arreza, M. O., Budomo, L. A., Pinlac, L. M., Juan, C. S., Chung, W. Y., & Sauli, Z. (2018). Full Custom Rail-to-Rail Self-Calibrating Comparator for Low Voltage Successive Approximation Register Analog-to-Digital Converter. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 10(1-14), 41–45. Retrieved from https://jtec.utem.edu.my/jtec/article/view/3989

Issue

Vol. 10 No. 1-14: Exploring Man-Machines Compliance in Sensors and Control Systems

Section

Articles

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