Full Custom Rail-to-Rail Self-Calibrating Comparator for Low Voltage Successive Approximation Register Analog-to-Digital Converter
Keywords:
ADC, Rail-to-Rail Comparator, SelfCalibrating Comparator, Novel Rail-to-Rail Self-Calibrating Comparator,Abstract
The demand for low power consuming devices is increasing, particularly that of wireless sensor networks (WSN). This study aims to address this problem by designing a novel rail-to-rail comparator for SAR ADC integrated with selfcalibration to null offset. In this study, rail-to-rail comparator, self-calibrating comparator, and rail-to-rail self-calibrating comparator are the circuits that will be designed, compared and analyzed. The three circuit designs were realized using the 0.18um CMOS technologyand has undergonePVT variations. The designed comparators all operate with a 1.8 V supply. In comparing and determining which circuit is the best in terms of their response, all the circuits will be compared based on six parameters to be measured thru the use of Simulation Program with Integrated Circuit Emphasis, also known as SPICE. The rail-to-rail comparator design resulted in an ICMR of 700mV. The self-calibratingcomparator design has a prominent value of 78dB for its CMRR. On the other hand, the novel rail-to-rail self-calibrating comparator design has highlighted a 5.15 V/us slew rate, with a power dissipation of only 22.40uW. A layout of the novel rail-to-rail self-calibrating comparator was also implemented which has a power dissipation 25.60uW and a slew rate of 4.16 V/us. It was found that the proposed design’s key features are stable performance over wide temperature ranges from 0°C up to 49°C, high value of slew rate and low power consumption without compromising its function.References
R. Kuo, H. Hong, “A 17nW, 0.5V, 500S/s, Rail-to-rail SAR ADC with 8.1 Effective Number of Bits”, International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2014, pp.1-4.
Hoonki Kim et al., “A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array”, IEEE International Conference on Electron Devices and Solid-State Circuits, 2008, pp. 1, 4.
A. Mesgarani et al., “Supply Boosting Technique for Designing Very Low-Voltage Mixed-Signal Circuits in Standard CMOS”, 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2010, pp. 893-896.
H. Majid, R. Musa, “Design and Implementation of a 10-bit SAR ADC”, International Journal of Electrical, Robotics, Electronics and Communications Engineering, 2013, Volume 7 No.10, pp.848-850.
M. Ng, “0.18 µm Low Voltage 12-Bit Successive-ApproximationRegister Analog-to-Digital Converter (SAR ADC)”, 3rd Asia Symposium on Quality Electronic Design, 2011, pp. 277-280.
Song, L. et al, “An Ultra Low-Power Rail-to-Rail Comparator for ADC Designs”, 2011, pp.1-2.
Chin, SM., Hsieh, C.H., “A New Rail-to-Rail Comparator with Adaptive Power Control for Low Power SAR ADCs in Biomedical Application”, International Symposium Circuits And Systems (ISCAS), 2010, pp.1575-1576.
Jjj Akbari, M., Nejad-MM., Mirbozorgi S.A., “A New Rail-to-Rail Ultra Low Voltage High Speed Comparator”, 2013, pp.1.
Rabuske, T., Rabuske, F., Fernandes, J., Rodrigues, C., “An 8-bit 0.35- V 5.04- fJ/Conversion-Step SAR ADC With Background SelfCalibration of Comparator Offset”, 2014, pp.1-7.
Saisundar, S., Cheong, J.H., Je, M.“A 1.8V 1MS/s Rail-to-Rail 10-bit SAR ADC in 0.18μm CMOS”, 2012, pp. 83-84.
Downloads
Published
How to Cite
Issue
Section
License
TRANSFER OF COPYRIGHT AGREEMENT
The manuscript is herewith submitted for publication in the Journal of Telecommunication, Electronic and Computer Engineering (JTEC). It has not been published before, and it is not under consideration for publication in any other journals. It contains no material that is scandalous, obscene, libelous or otherwise contrary to law. When the manuscript is accepted for publication, I, as the author, hereby agree to transfer to JTEC, all rights including those pertaining to electronic forms and transmissions, under existing copyright laws, except for the following, which the author(s) specifically retain(s):
- All proprietary right other than copyright, such as patent rights
- The right to make further copies of all or part of the published article for my use in classroom teaching
- The right to reuse all or part of this manuscript in a compilation of my own works or in a textbook of which I am the author; and
- The right to make copies of the published work for internal distribution within the institution that employs me
I agree that copies made under these circumstances will continue to carry the copyright notice that appears in the original published work. I agree to inform my co-authors, if any, of the above terms. I certify that I have obtained written permission for the use of text, tables, and/or illustrations from any copyrighted source(s), and I agree to supply such written permission(s) to JTEC upon request.
