The Effect of Gate-Induced Drain Leakage (GIDL) on Scaled MOSFETS of Low Power Consumptions

Abstract

This project is aimed to study the impact of GateInduced Drain Leakage (GIDL) on scaled Metal-OxideSemiconductor Field-Effect Transistor (MOSFET) for low power efficient application. The MOSFET is operated with low power consumption. Microchip industries are undergoing an evolution where the size of a device is getting smaller, but the performance is great. Thus, this project studies the leakage mechanism in terms of the GIDL current on MOSFET that operates for low power and its physical size had been reduced. The output of this project will determine on what is the implications of GIDL on the performance of MOSFET with various sizes that been supplied with low voltage power. The characteristic of GIDL was studied and from those characteristics, MOSFET design parameters were proposed by referring to the International Technology Roadmap for Semiconductors (ITRS), 2011 edition. DEVEDIT and Atlas application in Silvaco TCAD software was used in this project. Three MOSFET with different physical gate length and several other parameters were designed in DEVEDIT application, then being simulated for data extraction in Atlas application. From the data extracted, it shows that as the size of MOSFET physical gate length become smaller, the leakage current tends to be higher. Apart from GIDL current (IGIDL) value, the “ON” current (ION) value and threshold voltage (VTH) value also been extracted for all MOSFET designs.