Optimization of the Running Speed of Ant Colony Algorithm with Address-based Hardware Method

Abstract

Ant colony algorithm is an algorithm inspired by the Nature. It has been used a lot for solving complex issues and finding optimum answers. However, this algorithm is problematic due to its huge calculations, resulting in the decrease of its running speed. Such a decrease is considered a weak point for the much used algorithm. This paper presents an optimized core design purely based on hardware technology. By presenting a special algorithm which runs on a programmable chip based on nodes' address in memory, the repetition of the same function is avoided. Assessments done on ISE Xilinx area have optimized the speed of the suggested Ant colony algorithm running time compared to the hardware method based on the population for 27 times, method based on ID 17.74 times, and the compound hardware-software method up to 15.71 times