ROM-Less Fully Digital Synthesizer Design, Based on Novel phase to Sinusoidal Interface

Abstract

An 8-bit fully digital synthesizer is proposed in this paper. Utilizing a phase to sinusoidal code interface is the outstanding difference of this structure versus its other counterparts. In order to achieve higher operation speed an 8 bit pipeline accumulator is used in proposed structure. The phase to sinusoidal interface along with linear DAC makes the Direct Digital Synthesizer (DDS) needless of conventionally used ROM look up table memory. Meanwhile the ASIC sine weighted DAC which requires specifically handled dynamic element matching (DEM) procedure and sophisticated layout techniques to enhance the resolution in accordance with the DDS specifications is eliminated. The intrinsic thermometric nature of the utilized phase to sinusoidal converter makes the system needless of binary to thermometer block required for segmented DACs. While simplifying the DDS overall configuration, the proposed structure makes it also possible to use the sinusoidal digital codes to be compared with sampled form of original signal and hence can eliminate analog comparison in the front end stage. To evaluate the performance of the proposed circuit, it is initially simulated at system-level by Matlab and then it is implemented at logical gate level using Xilinx ISE environment and finally is practically realized by Xilinx SPARTAN 3 FPGA and its performance is evaluated experimentally.