ROM-Less Fully Digital Synthesizer Design, Based on Novel phase to Sinusoidal Interface

Authors

  • Hesam Pashaei Engineering Faculty, Department of Electrical and Electronic Engineering, Azarbaijan Shahid Madani University, Tabriz, Iran
  • Khalil Monfaredi Engineering Faculty, Department of Electrical and Electronic Engineering, Azarbaijan Shahid Madani University, Tabriz, Iran

Keywords:

Phase Accumulator (PA), Digital To Analog Converter (DAC), Direct Digital Synthesizer (DDS), ROM-less DDS, Phase To Sinusoidal Interface,

Abstract

An 8-bit fully digital synthesizer is proposed in this paper. Utilizing a phase to sinusoidal code interface is the outstanding difference of this structure versus its other counterparts. In order to achieve higher operation speed an 8 bit pipeline accumulator is used in proposed structure. The phase to sinusoidal interface along with linear DAC makes the Direct Digital Synthesizer (DDS) needless of conventionally used ROM look up table memory. Meanwhile the ASIC sine weighted DAC which requires specifically handled dynamic element matching (DEM) procedure and sophisticated layout techniques to enhance the resolution in accordance with the DDS specifications is eliminated. The intrinsic thermometric nature of the utilized phase to sinusoidal converter makes the system needless of binary to thermometer block required for segmented DACs. While simplifying the DDS overall configuration, the proposed structure makes it also possible to use the sinusoidal digital codes to be compared with sampled form of original signal and hence can eliminate analog comparison in the front end stage. To evaluate the performance of the proposed circuit, it is initially simulated at system-level by Matlab and then it is implemented at logical gate level using Xilinx ISE environment and finally is practically realized by Xilinx SPARTAN 3 FPGA and its performance is evaluated experimentally.

Author Biography

Hesam Pashaei, Engineering Faculty, Department of Electrical and Electronic Engineering, Azarbaijan Shahid Madani University, Tabriz, Iran

Dr. Khalil Monfaredi received the B.Sc., M.Sc., and PhD degrees from Tabriz University in 2001 and Iran University of Science and Technology in 2003 and 2011, respectively. He was with Electronic Research Center Group, during 2001 to 2011 and was also an academic staff with Islamic Azad University, Miyandoab Branch from 2006 to 2012. He served as the Research and Educational Assistant of Miyandoab Sama College from 2009 to 2011 and vice chancellor during 2011 to 2012. He is currently with Electrical and Electronics Engineering Faculty, Azarbaijan Shahid Madani University, Tabriz 5375171379, Islamic Republic of Iran. He is the author or coauthor of more than thirty national and international papers and also collaborated in several research projects. He is also the founder of electronic department in Islamic Azad University-Miyandoab Branch and was the chairman of 2010 electronic and computer scientific conference (ECSC2010) held in Islamic Azad University, Miyandoab Branch. His current research interests include current mode integrated circuit design, low voltage, low power circuit and systems and analog microelectronics and data converters.

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Published

2017-09-29

How to Cite

Pashaei, H., & Monfaredi, K. (2017). ROM-Less Fully Digital Synthesizer Design, Based on Novel phase to Sinusoidal Interface. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 9(3), 155–161. Retrieved from https://jtec.utem.edu.my/jtec/article/view/1487

Issue

Vol. 9 No. 3: July - September 2017

Section

Articles

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