Design of Gain Booster for Sample and Hold Stage of High Speed-Low Power Pipelined Analog-to-Digital Converter

Authors

  • Mohd Hafiz Jali

Keywords:

Gain Boost, Folded cascode, Sample and Hold Amplifier, Pipelined ADC

Abstract

This paper presents the full custom design of an operational transconductance amplifier (OTA) for the sample and hold (SHA) stage of a 10-bit 50-MS/s pipelined analog-todigital converter (ADC) implemented in a TSMC 0.35μm CMOS process. The OTA chosen for this design is folded cascode with gain boost topology. It is demonstrated through the design analysis and HSPICE simulation that such a structure realizes the best trade-off between power, speed and gain. The simulation results show the OTA achieves DC gain of 88.05dB, unity gain bandwidth of 430.03MHz and 84.06 degree of phase margin. The OTA achieves 62.13 dB SNR at the sampling rate of 50MHz with the input frequency of 24MHz. Power consumption is 9.68 mW from a single 3V supply. The settling time to 2-11 accuracy is 8.2ns.

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How to Cite

Jali, M. H. (2013). Design of Gain Booster for Sample and Hold Stage of High Speed-Low Power Pipelined Analog-to-Digital Converter. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 5(1), 23–29. Retrieved from https://jtec.utem.edu.my/jtec/article/view/481

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Section

Articles