Implementation of a 4-bit Ripple Carry Full Adder of Mirror Design Style Using Synopsys Generic 90nm Technology on a Full-Custom and Semi-Custom Design

Authors

  • Noel B. Linsangan School of Electronics, Electrical and Computer Engineering, Mapúa University, Intramuros 658 Muralla St., Intramuros, Manila 1002, Philippines.
  • Kenji J. Yabashi School of Electronics, Electrical and Computer Engineering, Mapúa University, Intramuros 658 Muralla St., Intramuros, Manila 1002, Philippines.
  • Ramon G. Garcia School of Electronics, Electrical and Computer Engineering, Mapúa University, Intramuros 658 Muralla St., Intramuros, Manila 1002, Philippines.
  • Arnold C. Paglinawan School of Electronics, Electrical and Computer Engineering, Mapúa University, Intramuros 658 Muralla St., Intramuros, Manila 1002, Philippines.
  • Marloun P. Sejera School of Electronics, Electrical and Computer Engineering, Mapúa University, Intramuros 658 Muralla St., Intramuros, Manila 1002, Philippines.
  • Charmaine C. Paglinawan School of Electronics, Electrical and Computer Engineering, Mapúa University, Intramuros 658 Muralla St., Intramuros, Manila 1002, Philippines.
  • Zaliman Sauli School of Microelectronic Engineering, Universiti Malaysia Perlis, Pauh Putra Campus, 02600 Arau, Perlis, Malaysia.

Keywords:

Full Adder, Layout Diagram, Schematic Diagram, Verification Process,

Abstract

The most frequently used component in the datapath block and the speed-limiting element is the adder. Because of this, it is essential to optimize the adder knowing it has a big impact on the overall system performance. In addition to that, adders are a very important subsystem in digital designs, thus, taking care about its performance must be spotted. By manipulating the transistor sizes and circuit topology, the speed can be optimized. A circuit of a CMOS (Complementary metal oxide semiconductor) 4-bit RCA (Ripple Carry Adder) is presented. The proposed adder cell refers to the CMOS adder class executed on CMOS mirror design style that has a smaller area and delay compared with the static adder implementation of the full adder. By simply cascading full-adder blocks, one obtains a Ripple-Carry Adder which perhaps the simplest to implement than that of the other carry adders. Creating the full adder in schematic diagram is a part of Pre-simulation. It incorporates the construction of CMOS transistors and connected through the use of wires. Widths and lengths of the transistors are the crucial parts in designing to place and route connections easily. Layout diagram is the equivalent of the schematic diagram but more on a detailed part and it should be the same as the transistor based circuit. With the aid of the verification processes such as DRC (Design Rule Check) and LVS (Layout versus Schematic), it can give an assurance that both the schematic and layout diagrams are similar and functioning properly.

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Published

2018-05-30

How to Cite

Linsangan, N. B., Yabashi, K. J., Garcia, R. G., Paglinawan, A. C., Sejera, M. P., Paglinawan, C. C., & Sauli, Z. (2018). Implementation of a 4-bit Ripple Carry Full Adder of Mirror Design Style Using Synopsys Generic 90nm Technology on a Full-Custom and Semi-Custom Design. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 10(1-14), 31–34. Retrieved from https://jtec.utem.edu.my/jtec/article/view/3987

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