Energy-Efficient Performance-Aware Fair Memory Access Scheduling on Multicore Platform (EEPAF)

Authors

  • Aastha Modgil Department of CSE and IT, Jaypee University of Information Technology Waknaghat, Solan 173234, H.P.,India.
  • Vivek Kumar Sehgal Department of CSE and IT, Jaypee University of Information Technology Waknaghat, Solan 173234, H.P.,India.

Keywords:

Energy Efficiency, Memory Access Scheduler SDRAM, Thread Fairness,

Abstract

In current scenario, energy consumption, performance and capacity of the main memory system are key factors that affect the design of a computing system. These days, computing systems are facilitated with multiple cores. Multicore system enables simultaneous execution of multiple applications. These concurrently running applications interfere at main memory. Main memory is a major resource demanded by running threads because it stores data structures that are required for execution of an application. Main memory energy consumption and performance can be improved by reducing the number of operations required to access its memory contents and by limiting the delay to service the memory access. It can be achieved by intelligently scheduling the memory requests and it is underlying memory access scheduler that decides the scheduling of memory accesses. This paper proposes a memory access scheduling scheme, EEPAF, for reducing the energy consumption and improving the performance of main memory. EEPAF, prioritizes reads over writes, exploits row buffer hits, increases bank level parallelism, implement delayed write drain policy and ensures fairness among threads. The results quantify the main memory energy consumption for different workloads under varied core environment and demonstrate significant reduction in power consumption, energy-delay product, and execution time, while improving performance.

References

K. Barr and K. Asanovic, “Energy aware lossless data compression,” in 1st Int. Conf. Mobile Systems, Applications, and Services (MobiSys’03), San Francisco, CA, May 2003.

8 Kim, H., Vijaykrishnan, N., Kandemir, M., Brockmeyer, E., Catthoor, F., and Irwin, M.J.: ‘Estimating influence of data layout optimizations on SDRAM energy consumption’. Proc. ISLPED, Aug. 2003, pp. 40–43.

C. Lefurgy, K. Rajamani, F. Rawson, W. Felter, M. Kistler, and T. Keller. Energy management for commercial servers. IEEE Computer, 36(12):39–48, 2003.

K. Nesbit, N. Aggarwal, J. Laudon, and J. E. Smith, “Fair queuing memory systems,” in Proc. 39th Annu. IEEE/ACM Int. Symp. Microarchit., 2006, pp. 208–222.

T. Moscibroda and O. Mutlu, “Memory performance attacks: Denial of memory service in multi-core systems,” in Proc. 16th USENIX Security Symp. USENIX Security Symp., 2007, pp. 18:1– 18:18.

O. Mutlu and T. Moscibroda, “Stall-time fair memory access scheduling for chip multiprocessors,” in Proc. 40th Annu. IEEE/ ACM Int. Symp. Microarchit., 2007, pp. 146–16.

O. Mutlu and T. Moscibroda, “Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared DRAM systems,” in Proc. 35th Annu. Int. Symp. Comput. Archit., 2008, pp. 63–74.

S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D. Owens, “Memory access scheduling,” in Proc. 27th Annu. Int. Symp. Comput. Archit., 2000, pp. 128–138.

JEDEC, Standard No. 79-3. DDR3 SDRAM STANDARD, 2010.

Y. Kim, V. Seshadri, D. Lee, J. Liu, and O. Mutlu, “A case for exploiting subarray-level parallelism (SALP) in DRAM,” in Proc. 39th Annu. Int. Symp. Comput. Archit., 2012, pp. 368–379.

D. Lee, Y. Kim, V. Seshadri, J. Liu, L. Subramanian, and O. Mutlu, “Tiered-latency DRAM: A low latency and low cost DRAM architecture,” in Proc. IEEE 19th Int. Symp. High Perform. Comput. Archit., 2013, pp. 615–626.

D. Lee, K. Yoongu, G. Pekhimenko, S. Khan, V. Seshadri, K. Chang, and O. Mutlu, “Adaptive-latency DRAM: Optimizing DRAM timing for the common-case,” in Proc. IEEE 21st Int. Symp. High Perform. Comput. Archit., 2015, pp. 489–50.

V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, P. Gibbons, M. Kozuch, and T. Mowry, “RowClone: Fast and efficient In-DRAM copy and initialization of bulk data,” in Proc. 46th Annu. IEEE/ACM Int. Symp. Microarchit., 2013, pp. 185–197.

Y. Kim, M. Papamichael, O. Mutlu, and M. Harchol-Balter, “Thread cluster memory scheduling: Exploiting differences in memory access behavior,” in Proc. MICRO, 2010.H. Simpson, Dumb Robots, 3rd ed., Springfield: UOS Press, 2004, pp.6-9.

M. Bojnordi and E. Ipek, “PARDIS: A programmable memory controller for the DDRx interfacing standard,” in Proceedings of ISCA, 2012.

Aastha Modgil, Nitin and Vivek Kumar Sehgal,“Understanding and Analyzing the Impact of Memory Controller’s Scheduling Policies on DRAM’s Energy and Performance,” in proceedings of the 4th ICECCS, 2015, vol. 70, pp.399-406

J. Shao and B. T. Davis, “A burst scheduling access reordering mechanism”, In HPCA-13, 2007

I. Hur and C. Lin., “Adaptive history-based memory schedulers”, in MICRO-37, 2004.

Long Chen, Yanan Cao, Sarah Kabala and Parijat Shukla, “Pre-Read and Write-Leak Memory Scheduling Algorithm,” in 3rd JILP Workshop on Computer Architecture Competitions: Memory Scheduling Championship, MSC, 2012.

Y. Kim, D. Han, O. Mutlu, and M. Harchol-Balter, “ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers,” in Proc. HPCA, 2010.

Y.S. Moon, Y. Kwon, H.S. Kim, D. Kim, H. H. Lee and K. Park, “The Compact Memory Scheduling Maximizing Row Buffer Locality,” in 3rd JILP Workshop on Computer Architecture Competitions: Memory Scheduling Championship, MSC, 2012.

Li, C., Wang, D., Wang, H., & Xue, Y. Priority Based Fair Scheduling: A Memory Scheduler Design for ChipMultiprocessor Systems. Tsinghua National Laboratory for Information Science and Technology.

Fang, K., Iliev, N., Noohi, E., Zhang, S., Zhu, Z.; 2012.; “Thread-Fair Memory Request Reordering,” 3rd JILP Workshop on Computer Architecture Competitions(JWAC-3): Memory Scheduling Championship (MSC), July 2012.

Z. Zhu and Z. Zhang, “A performance comparison of dram memory system optimizations for smt processors,” in Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA), pages 213 – 224, Feb. 2005.

J. W. Janzen. TN-46-03 - Calculating Memory System Power for DDR. Micron Technology, Inc., October 2003.

Micron Technology Inc. Calculating Memory System Power for DDR3 - Technical Note TN-41-01, 2007

Micron System Power Calculator. http://goo.gl/4dzK6.

Micron Technology, Inc., 2004. Calculating memory system power for DDR2. Technical Note, http://www.micron.com.

N. Chatterjee, R. Balasubramonian, M. Shevgoor, S. Pugsley, A. Udipi, A. Shafiee, K. Sudan, M. Awasthi, and Z. Chishti, “USIMM: the Utah SImulated Memory Module,” Technical report, University of Utah, 2012. UUCS-12-002.

C. Bienia, S. Kumar, J. P. Singh, and K. Li., “The PARSEC Benchmark Suite: Characterization and Architectural Implications,” in Proceedings of PACT, 2008.

R. Gonzalez and M. Horowitz, “Energy Dissipation in General Purpose Processors,” in Proceedings of the IEEE Symposium on Low Power Electronics, Oct. 1995, pp. 12-3.

M. A.Bender, S.Chakrabarti, and S. Muthukrishnan, “Flow and stretch metrics for scheduling continuous job streams,” in Proceedings of the ACM Symposium on Discrete Algorithms (SODA), 1998.

Downloads

Published

2017-11-23

How to Cite

Modgil, A., & Sehgal, V. K. (2017). Energy-Efficient Performance-Aware Fair Memory Access Scheduling on Multicore Platform (EEPAF). Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 9(3-6), 61–66. Retrieved from https://jtec.utem.edu.my/jtec/article/view/3046