A Preliminary Study of Characterization Techniques for Reticle ESD Threshold Voltage Measurement


  • H. Razman Silterra Malaysia Sdn. Bhd.
  • A.A.M. Isa Faculty of Electronic and Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka (UTeM), Malaysia.
  • W.A.A.W. Razali Silterra Malaysia Sdn. Bhd.
  • M.K. Suaidi Faculty of Electronic and Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka (UTeM), Malaysia.
  • M.S.I.M. Zin Faculty of Electronic and Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka (UTeM), Malaysia.


Characterization, Reticle, ESD, Threshold voltage


Recent studies have revealed that reticle robustness towards electrostatic field is reducing since the feature’s critical dimension is getting smaller. Reticle electrostatic damage is seen after the features was subjected at low Electrostatic Discharged (ESD) voltages. This characterization was conducted on a Chrome-on-glass (COG)/Binary reticle metal layer for Complementary Metal-Oxide Semiconductor (CMOS) 250nm technology node. International Technology Roadmap for Semiconductor (ITRS) and Semiconductor Equipment and Materials International (SEMI) uses the results of this reticle electrostatic damaged characterization, extrapolates it and establishes electrostatic field limits for semiconductor industry. Generally, a semiconductor wafer fabrication company will refer to this guideline to set up an Electrostatic Protective Area (EPA) for the expansion of current facilities or new facilities. As CMOS technology node shrinks further to 130nm, the photolithography process becomes more challenging since it requires printing smaller features accurately. A newly advanced reticle, called PSM (Phase-shift Mask) reticle has been introduced. PSM reticle features are made of Molybdenum Silicide (MoSi) material, which is different from the Binary reticle that uses Chromium. Existing guideline for electrostatic control limit from ITRS and SEMI may not be sufficient to protect PSM reticle from ESD damaged due to the different material features and the smaller critical dimension (gap distance between two parallel lines). This paper proposed a future work for characterizing PSM reticle ESD threshold voltage measurement and documented the result in ITRS and SEMI as separate guideline. This study will benefit semiconductor industry to implement more accurate EPA according to reticle type and technology node. The previous characterization techniques will be reviewed and critically compared in order to gain a better understanding of the reticle ESD damaged mechanism and propose new techniques for characterizing reticle that reflect actual production environment, the latest features material and lower technology node.

Author Biography

H. Razman, Silterra Malaysia Sdn. Bhd.

Working in Silterra Malaysia Sdn Bhd as Quality Manager. An engineering doctorate student in Universiti Teknikal Malaysia Melaka.


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How to Cite

Razman, H., Isa, A., Razali, W., Suaidi, M., & Zin, M. (2016). A Preliminary Study of Characterization Techniques for Reticle ESD Threshold Voltage Measurement. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 8(1), 53–57. Retrieved from https://jtec.utem.edu.my/jtec/article/view/678

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