Design and Development of Deep Learning Convolutional Neural Network on an Field Programmable Gate Array

Authors

  • Y.C. Wong Micro and Nano Electronic (MINE) Research Group, Centre for Telecommunication Research & Innovation (CeTRI) Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia
  • Y.Q. Lee Micro and Nano Electronic (MINE) Research Group, Centre for Telecommunication Research & Innovation (CeTRI) Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia

Keywords:

Convolutional Neural Network, Field Programmable Gate Array,

Abstract

This paper presents the design and development of Convolutional Neural Network on Field Programmable Gate Array. In the recent work of deep learning Convolutional Neural Network, CNN is a challenging research area in both software and hardware implementation. Software implementations tend to be prohibitively slow considering that most of the neural networks run on sequentially operation architecture. Thus, the objective of this work is to design and develop deep learning CNN on FPGA based on the premise that hardware implementations that perform parallel computation of each neuron in the layers can be made faster. This work focuses on handwriting recognition where the machine has the ability to receive and interpret intelligible handwritten input from the sources. The speed of the CNN implemented on an FPGA was analyzed. Digits and numbers were successfully recognized by the developed system.

References

J. Wang, J. Lin and Z. Wang, "Efficient Hardware Architectures for Deep Convolutional Neural Network," in IEEE Transactions on Circuits and Systems I, vol. 65, no. 6, 2018, pp. 1941-1953.

J. Matai, A. Irturk and R. Kastner, "Design and Implementation of an FPGA-based Real Time Face Recognition System". 19th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2011, pp. 97-100.

C. Wang, L. Gong, Q. Yu, X. Li, Y. Xie and X. Zhou, "DLAU: A Scalable Deep Learning Accelerator Unit on FPGA", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no.3, 2017, pp. 513-517.

Y. Zhou, S. Redkar and X. Huang, "Deep Learning Binary Neural Network on an FPGA", 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2017, pp. 281- 284.

F. Yi, H. Xiao, S. Yongjie, "FPGA Accelerating Core Design Based on XNOR Neural Network algorithm", MATEC Web of Conference (SMIMA), 2018, pp. 1-5.

L. Ruo, "A framework for FPGA-Based Acceleration of Neural Network Inference with Limited Precision via High-Level Synthesis with Streaming Functionality", M.S. theses, University of Toronto, 2016.

Y. LeCun, C. Cortes, C.J.C. Burges, "MNIST handwritten digit database", [Online]. Available: http://yann.lecun.com/exdb/mnist/. [Accessed: 24- Aug- 2018].

J. Matai, A. Irturk and R. Kastner, "Design and Implementation of an FPGA-based Real Time Face Recognition System", 19th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2011, pp. 97-100.

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Published

2018-10-31

How to Cite

Wong, Y., & Lee, Y. (2018). Design and Development of Deep Learning Convolutional Neural Network on an Field Programmable Gate Array. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 10(4), 25–29. Retrieved from https://jtec.utem.edu.my/jtec/article/view/4116

Issue

Vol. 10 No. 4: October - December 2018

Section

Articles

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