Implementation of a Hardware-centric Vision System Architecture


  • Azman Muhamad Yusof Center of Excellence for Advance Sensor Technology (CEASTech), UniMAP. Department of Electronics Engineering Technology, Faculty of Engineering Technology, UniMAP.
  • Ali Yeon Md Shakaff Center of Excellence for Advance Sensor Technology (CEASTech), UniMAP. School of Mechatronic Engineering, UniMAP.
  • Saufiah Abdul Rahim School of Mechatronic Engineering, UniMAP.


Embedded Vision System, Hardware-Assisted Vision System, Image Processing Hardware, Machine Vision,


Currently, most implementations of vision systems still heavily rely on software - computer algorithms run on general purpose microprocessors, like on personal computers. This is understandable since personal computers (PC) are readily available, and software implementations provide flexibility, especially when trying out various algorithms. The need to have real-time vision-based systems influenced developers and researchers towards hardware-based - or at least hardware-assisted - vision systems that are capable of processing huge amount of data from an imaging device in realtime (i.e. embedded vision system). Platforms like DSPs, GPUs and FPGAs are among the commonly used development platforms for a hardware-centric vision system, while ASIC implementations - tagged with a huge development cost - usually have the best performance. This paper compares various possible platforms that are readily available and can be used to develop hardware-centric vision systems. This includes DSPs, GPUs and FPGAs, with some insights on ASIC implementation. Consequently, two implementations of the proposed hardwarecentric vision system architecture are presented. Both implementations managed to process incoming image stream from camera module at 30 frames per second.




How to Cite

Muhamad Yusof, A., Md Shakaff, A. Y., & Abdul Rahim, S. (2018). Implementation of a Hardware-centric Vision System Architecture. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 10(1-15), 123–129. Retrieved from