AES S-Box/ Inv S-Box Optimization Using FPGA Implementation

Authors

  • Hidayarni Hamzah Department of Electronic Engineering, Faculty of Electrical and Electronic Engineering, Universiti Tun Hussein Onn Malaysia, Parit Raja, Batu Pahat, Johor, Malaysia.
  • Nabihah Ahmad Department of Electronic Engineering, Faculty of Electrical and Electronic Engineering, Universiti Tun Hussein Onn Malaysia, Parit Raja, Batu Pahat, Johor, Malaysia.
  • M. Hairol Jabbar Department of Computer Engineering, Faculty of Electrical and Electronic Engineering, Universiti Tun Hussein Onn Malaysia, Parit Raja, Batu Pahat, Johor, Malaysia.
  • Chin Fhong Soon Department of Electronic Engineering, Faculty of Electrical and Electronic Engineering, Universiti Tun Hussein Onn Malaysia, Parit Raja, Batu Pahat, Johor, Malaysia.

Keywords:

AES, S-box/InvS-box, Composite Field, FPGA,

Abstract

Advanced Encryption Standard (AES) is a common symmetric encryption algorithm and widely implemented in Wireless Local Area Network (WLAN), Radio Frequency Identification (RFID) tags and Bluetooth controller as the default choice for security services in its application. Substitution box (S-box) is a non-linear transformation and the core of AES implementation which consumed most of the power in AES hardware. This paper presents a low-complexity design methodology for the S-box/ Inverse S-box (Inv S-box) implemented in Field-Programmable Gate Array (FPGA) using composite field arithmetic and Quartus II as a tool to obtain simulation results through Verilog Hardware Description Language (HDL). This design utilized 94 slices with the hardware cost of the S-box/InvS-box is about 172 logic gates, with the power consumption of 31mW and the throughput is 1.6Gbps obtained through calculation. The design is suitable for the portable device application which requires data security with a low area and power consumption.

References

National Inst. of Standards and Technology, “Federal Information Processing Standard Publication 197, the Advanced Encryption Standard (AES),”Nov.2001.

Ahmad N. 2016. New Architecture of Low Area Aes S-box/ Inv S-box Using VLSI Implementation.2016 Penerbit UTM Press Jurnal Teknologi.

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Ahmad N. and Hasan, R. 2012. Low-power compact composite field AES S-box/Inv S-box design in 65nm CMOS using Novel XOR Gate. Integration, the VLSI Journal, Available online ISSN 0167-9260, http://dx.doi.org/10.1016/j.vlsi. 2012. 06.002.R. C. Mikkelson (private communication).

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Mentens N., Batina L., Preneel B. and Verbauwhede I. 2005. A Systematic Evaluation Of Compact Hardware Implementations For The Rijndael S-box. Proceedings Of The 2005 International Conference on Topics in Cryptology. 323-333.

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Published

2017-11-30

How to Cite

Hamzah, H., Ahmad, N., Jabbar, M. H., & Soon, C. F. (2017). AES S-Box/ Inv S-Box Optimization Using FPGA Implementation. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 9(3-8), 133–136. Retrieved from https://jtec.utem.edu.my/jtec/article/view/3112

Issue

Vol. 9 No. 3-8: Recent Trend in Electronic, Computing and Communication

Section

Articles

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