Application of a Stable Latency Insertion Method for Simulations of Power Distribution Networks

Authors

  • Kin Hang Tan School of Electrical and Electronic Engineering, Universiti Sains Malaysia, 14300 Nibong Tebal, Pulau Pinang, Malaysia.
  • Patrick Goh School of Electrical and Electronic Engineering, Universiti Sains Malaysia, 14300 Nibong Tebal, Pulau Pinang, Malaysia.
  • Mohd Fadzil Ain School of Electrical and Electronic Engineering, Universiti Sains Malaysia, 14300 Nibong Tebal, Pulau Pinang, Malaysia.

Keywords:

Latency Insertion Method (LIM), On-Chip, Power Distribution Network,

Abstract

This paper presents an application of a stable implementation of the latency insertion method for simulations of power distribution networks (PDN). Traditionally, simulations of PDNs poses a considerable challenge due to their large circuit sizes. While the latency insertion method can be applied to simulate these networks, the existence of low latency elements results in a more stringent stability criterion which reduces the efficiency of the method. Using the improved formulation, a latency insertion method that is free from the stability criteria is obtained, which results in no limitation on the size of the time step.

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Published

2017-06-01

How to Cite

Hang Tan, K., Goh, P., & Ain, M. F. (2017). Application of a Stable Latency Insertion Method for Simulations of Power Distribution Networks. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 9(2-5), 27–31. Retrieved from https://jtec.utem.edu.my/jtec/article/view/2387

Issue

Vol. 9 No. 2-5: Circuit and System Advancement in Modern World IV

Section

Articles

License

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0)