The Implementation of an Efficient Zigzag Scan

Abstract

The continuous growth of multimedia data capacity and the large capacity of communication lines had always become the obstacle in communication of multimedia data. To overcome this, data compression process in a shorter time is required. One part of JPEG algorithm that is able to determine compression ratio and compression process speed is Zigzag Coding or Zigzag Scan algorithm. This research is focused on developing the zigzag scan algorithm with mapping method. Zigzag Scan with mapping method is a sorting process of DCT-quantized data result according to the position sequence determined in a zigzag. Implementation of the Zigzag Scan mapping method into FPGA using ROM that serves as zigzag address generator and RAM that serves to write (put) and read (issued) data according zigzag address generated by ROM. The efficiency of Zigzag Scan with mapping method has been successfully developed. It is able to accelerate the sorting process of DCT-quantized coefficients period because input data can be immediately located in sequence position which has been determined without any value comparison and repetition process. Zigzag Scan with mapping method process time is 250 MHz or approximately 4ns per byte data (12 ns per pixel) with the delay time (latency) by 64 clock. It means that the generated IC Zigzag Scan prototype can be operated in realtime JPEG/MPEG compression with a maximum of 3 mega pixel per frame for video with 25 fps speed. The generated IC Zigzag Scan component (IP Core) needs 10 slices of Flip-flop (30 times less than Arafa method and 2 times less than Ketul method) and LUTs as many as 39 slices (20 times less than Arafa method and 2 times less that Ketul method).