A Novel Ultra Low-Power 10T CNFET-Based Full Adder Cell Design in 32nm Technology

Authors

  • Mohammad Hossein Shafiabadi Sama Technical and Vocational Training College, Islamic Azad University, Islamshahr Branch, Islamshahr, Iran
  • Yavar Safaei Mehrabani Sama Technical and Vocational Training College, Islamic Azad University, Islamshahr Branch, Islamshahr, Iran

Keywords:

Full Adder Cell, Carbon Nanotube (CNT), Low-Power, 10 Transistor, Process Variation,

Abstract

Nowadays, energy consumption is the main concern in portable electronic systems such as laptops, smart mobile phones, personal digital assistances (PDAs) and so forth. Considering that the 1-bit Full adder cell has been the determinant circuit due to its wide usage in these systems, it affects the entire performance of the electronic system. In this paper, a novel low-power and low-energy 10 transistor (10T) Full Adder cell using NAND/NOR functions based on carbon nanotube field effect transistors (CNFETs) is presented. The proposed cell showed superiority in terms of power-delay product (PDP) compared to the other cells under different simulation condition, such as power supply, temperature, load and operating frequency variations. Moreover, a Monte Carlo (MC) simulation was conducted to study the reliability of the proposed cell against manufacturing process variations (i.e. the variations of diameters of carbon nanotubes). Simulations confirmed the robustness of the proposed cell.

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Published

2016-12-01

How to Cite

Shafiabadi, M. H., & Mehrabani, Y. S. (2016). A Novel Ultra Low-Power 10T CNFET-Based Full Adder Cell Design in 32nm Technology. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 8(9), 25–30. Retrieved from https://jtec.utem.edu.my/jtec/article/view/831

Issue

Vol. 8 No. 9: September - December 2016

Section

Articles

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