Simulation Study on Different Logic Families of NOT Gate Transistor Level Circuits Implemented Using Nano-MOSFETs

Abstract

In this paper, a simulation study has been done on logic NOT transistor circuits with four different logic families, namely: (i) nano-CMOS NOT gate, (ii) nano-MOSFET loaded ntype nano-MOSFET NOT gate, (iii) resistive loaded nanoMOSFET NOT gate, and (iv) pseudo nano-MOSFET NOT gate. The simulation tool used is WinSpice. All the n-type and p-type nano-MOSFETs have channel length (L) 10 nm with width (W) 125 nm or 250 nm, depending on the type of logic families. Simulated timing diagrams for input and output waveforms showed correct logical NOT gate operations for all four logic families. Additionally, the voltage transfer characteristic (VTC) curves have been plotted for all four logic families. From the VTC plots, logic swing (VLS), transition width (VTW), high noise margin (VNMH), low noise margin (VNML), high noise sensitivity (VNSH), low noise sensitivity (VNSL), high noise immunity (VNIH) and low noise immunity (VNIL) have been obtained. Analysis on these values indicated that all the four logic NOT gate families which consist of nano-transistors meet the NOT gate operation conditions. Drain current, intrinsic delay and dynamic power are discussed as the effects of down scaling. In conclusion, NOT gates made of nano-MOSFETs with nanometer dimensions are able to perform correct logical operations in the same way as NOT gates made up of conventional bulk MOSFETs as proven by timing diagrams and VTC plots.