Simulation Study on Different Logic Families of NOT Gate Transistor Level Circuits Implemented Using Nano-MOSFETs

Authors

  • Ooi Chek Yee Faculty of Information and Communication Technology, Universiti Tunku Abdul Rahman, Jalan Universiti, Bandar Barat, 31900 Kampar, Perak, Malaysia.
  • Lim Soo King Lee Kong Chian Faculty of Engineering and Science, Universiti Tunku Abdul Rahman, Jalan Sungai Long, Bandar Sungai Long, Cheras, 43000 Kajang, Selangor, Malaysia

Keywords:

Logic family, nano-MOSFET, NOT gate, simulation

Abstract

In this paper, a simulation study has been done on logic NOT transistor circuits with four different logic families, namely: (i) nano-CMOS NOT gate, (ii) nano-MOSFET loaded ntype nano-MOSFET NOT gate, (iii) resistive loaded nanoMOSFET NOT gate, and (iv) pseudo nano-MOSFET NOT gate. The simulation tool used is WinSpice. All the n-type and p-type nano-MOSFETs have channel length (L) 10 nm with width (W) 125 nm or 250 nm, depending on the type of logic families. Simulated timing diagrams for input and output waveforms showed correct logical NOT gate operations for all four logic families. Additionally, the voltage transfer characteristic (VTC) curves have been plotted for all four logic families. From the VTC plots, logic swing (VLS), transition width (VTW), high noise margin (VNMH), low noise margin (VNML), high noise sensitivity (VNSH), low noise sensitivity (VNSL), high noise immunity (VNIH) and low noise immunity (VNIL) have been obtained. Analysis on these values indicated that all the four logic NOT gate families which consist of nano-transistors meet the NOT gate operation conditions. Drain current, intrinsic delay and dynamic power are discussed as the effects of down scaling. In conclusion, NOT gates made of nano-MOSFETs with nanometer dimensions are able to perform correct logical operations in the same way as NOT gates made up of conventional bulk MOSFETs as proven by timing diagrams and VTC plots.

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Published

2016-08-01

How to Cite

Chek Yee, O., & Soo King, L. (2016). Simulation Study on Different Logic Families of NOT Gate Transistor Level Circuits Implemented Using Nano-MOSFETs. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 8(5), 61–67. Retrieved from https://jtec.utem.edu.my/jtec/article/view/765

Issue

Vol. 8 No. 5: May - August 2016

Section

Articles

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