Rapid Prototyping and Performance Evaluation of a MIMO CDMA System Using an FPGA-Based Hardware Platform

Authors

  • Mostafa Hefnawi

Keywords:

Rapid prototyping, FPGA, Hardware-in-the-loops, DS-CDMA, MIMO, Space-time coding, Rake receiver

Abstract

This paper investigates the rapid prototyping of a multiple input-multiple-output direct sequence-code division multiple access (MIMO DS-CDMA) system with rake receiver, implemented on a field programmable gate array (FPGA) based hardware platform. The hardware implementation is created using the Altera DSP builder– a MATLAB/Simulink based system-level design tool and the Stratix EP1S80 DSP development board from Altera. The hardware-in-the-loop (HIL) co-simulation and the Logic Analyzer are used with the physical FPGA board implementing the design to evaluate the system performance and to verify the functionality of the hardware implementation in the MATLAB/Simulink environment. Results show that, in general, the bit error rate (BER) of the hardware implementation fell within the confidence intervals of the simulated BER

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How to Cite

Hefnawi, M. (2016). Rapid Prototyping and Performance Evaluation of a MIMO CDMA System Using an FPGA-Based Hardware Platform. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 7(2), 13–17. Retrieved from https://jtec.utem.edu.my/jtec/article/view/608

Issue

Vol. 7 No. 2

Section

Articles

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