Design of an Efficient AXI-4 Protocol for High Speed SOC Applications on FPGA Platform
Keywords:
AHB, AMBA, ASB, AXI-4, Burst, FPGA, Master, Slave, SOC, Transaction,Abstract
The system-on-chip(SoC) design process encounters various challenges of communication between one to another module. Thus, the Bus interconnection plays a significant role in improving the system performance on a single chip. The traditional bus interconnections cease its applicability to meet the requirements of future generation SoC. This paper proposes an efficient design of the AXI-4 protocol to achieve high-speed data transfer in the SoC application. The proposed AXI-4 Interface protocol includes the Master and Slave module, which are designed using state flow and state diagrams. Both the Master and Slave module operations support burst based transactions and perform the five different channel transactions that include “write address,” “write data,” “write a response,” “read address,” “read data” along with “read response.” The simulation results of the AXI-4 interface and its FPGA realization on Artix-7 illustrate lower resource utilization, and the performance benchmarking between proposed AXI-4 with traditional AHB and Wishbone bus modules illustrates an average minimization in area and increase in frequency by 40% and 41% respectively.References
W. Su, J. Wang, H, Wang, and L. Wang, “An Optimized Solution for Cross-Domain System Bus Transaction Processing”, In Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD), 14th ACIS International Conference on IEEE, 2013, pp. 165-170.
Z. Li, J. Li, Y. Zhao, C. Rong, & J. Ma, “A SoC Design and Implementation of H. 264 Video Encoding System Based on FPGA”, In Intelligent Human-Machine Systems and Cybernetics (IHMSC), 2014 Sixth International Conference on IEEE, Vol. 2,2014, pp.321- 324.
S. Ramagond, S. Yellampalli and C. Kanagasabapathi, “A review and analysis of communication logic between PL and PS in ZYNQ AP SoC”, In 2017 International Conference on Smart Technologies for Smart Nation (Smart Tech-Con), 2017, pp. 946-951.
A. B. Mehta, “SoC Interconnect Verification”, In ASIC/SoC Functional Design Verification, Springer, Cham, 2018, pp. 273-284.
D.C. Liang, “Hard real-time bus architecture and arbitration algorithm based on AMBA”, 2015, pp. 1-7.
G. Mahesh and S.M. Sakthivel, “Functional verification of the Axi2OCP Bridge using system verilog and effective bus utilization calculation for AMBA AXI 3.0 protocol”, In Innovations in Information, Embedded and Communication Systems (ICIIECS), International Conference on IEEE, 2015, pp. 1-5.
P.R. Ronak and S. Jagtap, “Design and verification of flexible interface for multicore system using PCIe IO virtualization”, In Recent Trends in Electronics, Information & Communication Technology (RTEICT), IEEE International Conference on IEEE, 2016, pp. 623-627.
AMBA, “AXI-Protocol Specification V2”, 0. ARM Holdings plc. Std, 2010.
C. Sarojini and J. Thangaraj “Implementation and Optimization of Throughput in High Speed Memory Interface Using AXI Protocol”, In 2018 9th International Conference on Computing, Communication, and Networking Technologies (ICCCNT), 2018, pp. 1-5.
N.Tidala, “High-Performance Network on Chip using AXI4 protocol interface on an FPGA”, In 2018 Second International Conference on Electronics, Communication and Aerospace Technology (ICECA), 2018, pp. 1647-1651.
E. Azarkhish, D. Rossi, I. Loi, and L. Benini,”High-performance AXI- 4.0 based interconnect for extensible smart memory cubes”, In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015, pp. 1317-1322.
M. Makni, M. Baklouti, S. Niar, and M. Abid, “Performance Exploration of AMBA AXI4 Bus Protocols for Wireless Sensor Networks”, In Computer Systems and Applications (AICCSA), 2017 IEEE/ACS 14th International Conference on IEEE, 2017, pp. 1163- 1169.
D.C. Kho and K. Munusamy, “Transaction-based SoC design techniques for AMBA AXI4 bus interconnects using VHDL”, In Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), 2014 11th International Conference on IEEE, 2014, pp. 1-6.
M. Gayathri, R. Sebastian, S.R. Mary, and A. Thomas, “A SV-UVM framework for verification of SGMII IP core with reusable AXI to WB Bridge UVC”, In Advanced Computing and Communication Systems (ICACCS), 3rd International Conference on IEEE, 2016, pp. 1-4.
R.H. Prasad and C.S. Rani, “Development of VIP for AMBA AXI-4.0 Protocol”, Indian Journal of Science and Technology, Vol.9, 2016, pp. 48.
S. Sharma, and S.M. Sakthivel, “Design and Verification of AMBA AXI3 Protocol”, In VLSI Design: Circuits, Systems, and Applications, Springer, Singapore, 2016, pp. 247-259.
Z. Panjkov, J. Haas, M. Aigner, H. Rosmanith, T. Liu, “Poppenreiter & R. Hagelauer, “OCP2XI Bridge: An OCP to AXI Protocol Bridge”, In International Symposium on Applied Reconfigurable Computing , 2016, pp. 179-190.
R. Bhaktavatchalu, B.S. Rekha, G.A. Divya, and V.U.S Jyothi, “Design of AXI bus interface modules on FPGA”, In Advanced Communication Control and Computing Technologies (ICACCCT), International Conference on IEEE, 2016, pp. 141-146.
H.R. Archana, and K.V. Patel, “A Novel Design and Implementation of Imaging Chip Using AXI Protocol for MPSOC on FPGA”, In Proceedings of the Computational Methods in Systems and Software Springer, Cham, 2018, pp. 44-57.
F. Benevenuti and F.L. Kastensmidt, “Reliability evaluation on interfacing with AXI and AXI-S on Xilinx Zynq-7000 AP-SoC”, In Test Symposium (LATS), IEEE 19th Latin-American, 2018, pp. 1-6.
A. Gaur, P. Sharma, and S.P. Pandey, “HDL and timing analysis of AMBA AHB on FPGA platform”, In Control, Automation & Power Engineering (RDCAPE), Recent Developments in IEEE, 2017, pp. 22- 27.
A.K. Swain, and K. Mahapatra, “Design and verification of WISHBONE bus interface for System-on-Chip integration”, In India Conference (INDICON), Annual IEEE, 2010, pp. 1-4
Downloads
Published
How to Cite
Issue
Section
License
TRANSFER OF COPYRIGHT AGREEMENT
The manuscript is herewith submitted for publication in the Journal of Telecommunication, Electronic and Computer Engineering (JTEC). It has not been published before, and it is not under consideration for publication in any other journals. It contains no material that is scandalous, obscene, libelous or otherwise contrary to law. When the manuscript is accepted for publication, I, as the author, hereby agree to transfer to JTEC, all rights including those pertaining to electronic forms and transmissions, under existing copyright laws, except for the following, which the author(s) specifically retain(s):
- All proprietary right other than copyright, such as patent rights
- The right to make further copies of all or part of the published article for my use in classroom teaching
- The right to reuse all or part of this manuscript in a compilation of my own works or in a textbook of which I am the author; and
- The right to make copies of the published work for internal distribution within the institution that employs me
I agree that copies made under these circumstances will continue to carry the copyright notice that appears in the original published work. I agree to inform my co-authors, if any, of the above terms. I certify that I have obtained written permission for the use of text, tables, and/or illustrations from any copyrighted source(s), and I agree to supply such written permission(s) to JTEC upon request.
