A Novel Differential Ramp Generator Circuit with PVT Compensation Structure

Authors

  • Mohsen Padash Department of Electrical Engineering, University of Zanjan, Zanjan, Iran.
  • Mostafa Yargholi Department of Electrical Engineering, University of Zanjan, Zanjan, Iran

Keywords:

Counter ADC, Differential Ramp Generator, PVT Compensation, Single Slope,

Abstract

Applications like counter ADC demanded accurate ramp signal with low power dissipation. This paper presents a novel approach of low power differential ramp generator with negative feedback for the compensation of the variations in process, voltage, and temperature (PVT). The derived equations of the proposed ramp generator circuit show that PVT compensation is enhanced significantly. Additionally, the circuit design and simulations were done in TSMC 0.18-μm CMOS technology. The Monte Carlo simulation results and corner analysis show that the linearity of the ramp signal is about 9-bit while power dissipation of the circuit is about 2.61μW.

References

J. Xu, J. Yu, F. Huang, and K. Nie, "A 10-Bit Column-Parallel Single Slope ADC Based on Two-Step TDC with Error Calibration for CMOS Image Sensors," Journal of Circuits, Systems and Computers, vol. 24, p. 1550054, 2015.

L. Junan, P. Himchan, S. Bongsub, K. Kiwoon, E. Jaeha, K. Kyunghoon, et al., "High Frame-Rate VGA CMOS Image Sensor Using Non-Memory Capacitor Two-Step Single-Slope ADCs," Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 62, pp. 2147-2155, 2015.

Y. Hwang, S. Lee, and M. Song, "Design of a CMOS image sensor with a 10-bit two-step single-slope A/D converter and a hybrid correlated double sampling," in Microelectronics and Electronics (PRIME), 2014 10th Conference on Ph. D. Research in, 2014, pp. 1-4.

S. Naraghi, M. Courcy, and M. P. Flynn, "A 9-bit, 14 μW and 0.06 mm2 Pulse Position Modulation ADC in 90 nm Digital CMOS," Solid-State Circuits, IEEE Journal of, vol. 45, pp. 1870-1880, 2010.

M. Padash and M. Yargholi, "A novel time-interleaved two-step singleslope ADC architecture based on both resistor ladder and current source ramp generator," Microelectronics Journal, vol. 61, pp. 67-78, 2017.

G. Wu, G. Deyuan, W. Tingcun, C. Hu-Guo, and H. Yann, "A 12-bit low-power multi-channel ramp ADC using digital DLL techniques for high-energy physics and biomedical imaging," in Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on, 2010, pp. 227-229.

C. J. Hyunho, Kim; Chulwoo, Kim, "A monolithic voltage-mode DCDC converter with a novel oscillator and ramp generator," IEICE Electronics Express, vol. 5, p. 5, 10.09.2008 2008.

B. D. Tsirigotis Georgios, "Comparative Control of a Nonlinear First Order Velocity System by a Neural Network NARMA-L2 Method," ELEKTRONIKA IR ELEKTROTECHNIKA, vol. 55, pp. 5-8, 2004.

B. Provost and E. Sanchez-Sinencio, "On-chip ramp generators for mixed-signal BIST and ADC self-test," Solid-State Circuits, IEEE Journal of, vol. 38, pp. 263-273, 2003.

K. V. Tham, C. Ulaganathan, N. Nambiar, R. L. Greenwell, C. L. Britton, M. N. Ericson, et al., "PVT Compensation for Wilkinson Single-Slope Measurement Systems," Nuclear Science, IEEE Transactions on, vol. 59, pp. 2444-2450, 2012.

I. Sordo, x, x00F, S. ez, S. Espejo-Meana, Pi, et al., "Four-channel selfcompensating single-slope ADC for space environments," Electronics Letters, vol. 50, pp. 579-581, 2014.

M. F. Snoeij, A. J. P. Theuwissen, K. A. A. Makinwa, and J. H. Huijsing, "Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors," Solid-State Circuits, IEEE Journal of, vol. 42, pp. 2968-2977, 2007.

S. Danesh, J. Hurwitz, K. Findlater, D. Renshaw, and R. Henderson, "A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly TimeInterleaved Counter ADC with Low Power Comparator Design," SolidState Circuits, IEEE Journal of, vol. 48, pp. 733-748, 2013.

M. Padash and M. Yargholi, "Positive and Negative Feedback for Linearity Improvement and PVT Compensation of the Ramp Generator," Journal of Circuits, Systems and Computers, vol. 28, p. 23, 2019.

M. Padash and M. Yargholi,, "Linearity and Stability Improvement of the Ramp Generator with Low Power Consumption for Single-Slope ADCs," TABRIZ JOURNAL OF ELECTRICAL ENGINEERING, vol. 48, pp. 531-539, 2018.

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Published

2020-03-31

How to Cite

Padash, M., & Yargholi, M. (2020). A Novel Differential Ramp Generator Circuit with PVT Compensation Structure. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 12(1), 63–67. Retrieved from https://jtec.utem.edu.my/jtec/article/view/5721