Analysis of Gate Poly Delayering in SOI Wafer

Authors

  • Handie Ahmataku X-FAB Sarawak Sdn. Bhd., 1 Silicon Drive, Samajaya Free Industrial Zone, 93350 Kuching, Sarawak, Malaysia
  • Shahrol Mohamaddan Department of Mechanical and Manufacturing, Faculty of Engineering, Universiti Malaysia Sarawak (UNIMAS), 94300 Kota Samarahan, Sarawak, Malaysia.
  • Emilda Warren X-FAB Sarawak Sdn. Bhd., 1 Silicon Drive, Samajaya Free Industrial Zone, 93350 Kuching, Sarawak, Malaysia
  • Mahshuri Yusuf Department of Mechanical and Manufacturing, Faculty of Engineering, Universiti Malaysia Sarawak (UNIMAS), 94300 Kota Samarahan, Sarawak, Malaysia.
  • Aidil Azli Alias Department of Mechanical and Manufacturing, Faculty of Engineering, Universiti Malaysia Sarawak (UNIMAS), 94300 Kota Samarahan, Sarawak, Malaysia.
  • Nor Hasmaliana Abdul Manas Department of Chemical and Energy Sustainability, Faculty of Engineering, Universiti Malaysia Sarawak (UNIMAS), 94300 Kota Samarahan, Sarawak, Malaysia.
  • Kuryati Kipli Department of Electrical and Electronics, Faculty of Engineering, Universiti Malaysia Sarawak (UNIMAS), 94300 Kota Samarahan, Sarawak, Malaysia.

Keywords:

SOI, Top Silicon, Physical Failure Analysis, Bulk CMOS,

Abstract

The advantages of silicon-on-insulator (SOI) technology are reduced parasitic device capacitance, improved performance as well as smaller build area. Despite the gains of SOI technology to manufacturers, new challenges arise in Physical Failure Analysis (PFA). The process of delayering polysilicon or active layer becomes impossible without harming the top silicon. This study discussed the challenges of the current fastest, reliable and reproducible method to delayer polysilicon and divulge active layer. Current delayering method using 49% Hydrofluoric (HF) concentration and SC1 solution is proven to be a faster way to reveal polysilicon layer for Bulk Commentary Metal-Oxide Semiconductor (Bulk CMOS). Thus, this method was tested on SOI Wafer to analyze the effect. The experiment was conducted by selecting small, thin and dense gate polysilicon such as in Static Random Access Memory (SRAM) cells. The result shows that high concentration of HF is not suitable for SOI since HF will etch Interlayer Dielectric (ILD) all the way down to Buried Oxide (BOX) and leave top silicon unattached. As a result, top silicon structure was peeled off or damaged. The result was not promising since the top silicon is crucial part as it holds information to discover physical cause of failure.

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Published

2018-03-01

How to Cite

Ahmataku, H., Mohamaddan, S., Warren, E., Yusuf, M., Alias, A. A., Abdul Manas, N. H., & Kipli, K. (2018). Analysis of Gate Poly Delayering in SOI Wafer. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 10(1-12), 85–87. Retrieved from https://jtec.utem.edu.my/jtec/article/view/3831

Issue

Vol. 10 No. 1-12: Gearing for a Greener Future

Section

Articles

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