FPGA Implementation of Simulated Kalman Filter Optimization Algorithm

Authors

  • Nurul H. Noordin Faculty of Electrical and Electronic, Universiti Malaysia Pahang 26600 Pekan, Pahang Darul Makmur, Malaysia
  • Z. Ibrahim Faculty of Electrical and Electronic, Universiti Malaysia Pahang 26600 Pekan, Pahang Darul Makmur, Malaysia
  • M. H. J. Xie Faculty of Electrical and Electronic, Universiti Malaysia Pahang 26600 Pekan, Pahang Darul Makmur, Malaysia
  • R. Samad Faculty of Electrical and Electronic, Universiti Malaysia Pahang 26600 Pekan, Pahang Darul Makmur, Malaysia
  • N. Hasan Faculty of Electrical and Electronic, Universiti Malaysia Pahang 26600 Pekan, Pahang Darul Makmur, Malaysia

Keywords:

FPGA Design, Simulated Kalman Filter Optimization Algorithm,

Abstract

Optimization is listed as one of the important topics in today’s electronic system due to the presence of many non-linear problems in our daily life. The ability of these optimisation algorithms to perform in a real-time environment is crucial. This paper presents a novel FPGA implementation of the Simulated Kalman Filter Optimisation Algorithm. This system utilizes a distributed RAM to update the intermediate variables and the output of each iteration is stored in the block RAM. The address of the block RAM is displayed on the LCD. The hardware performance of the SKF is then compared to the PSO. Results show that the SKF has higher processing speed as well as less number of logic blocks and IO blocks were utilised.

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Published

2018-01-22

How to Cite

Noordin, N. H., Ibrahim, Z., Xie, M. H. J., Samad, R., & Hasan, N. (2018). FPGA Implementation of Simulated Kalman Filter Optimization Algorithm. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 10(1-3), 21–24. Retrieved from https://jtec.utem.edu.my/jtec/article/view/3480