High Speed Low Power CMOS Comparator using Forward Body Bias Technique in 0.13 µm Technology

Abstract

This paper presents the design of high speed and low power CMOS comparator using a forward body bias technique in 0.13-µm technology. Three types of CMOS comparators’ topologies have been designed in order to compare the performances of speed and power with the conventional comparator. Based on the analysis, the double-tail dynamic comparator is chosen since it shows better performance for high speed and low power. Therefore, a modified high-speed, low power double-tail dynamic comparator is proposed by using a forward body bias technique in order to reduce the supply voltage. The proposed dynamic comparator is implemented in Silterra 0.13-μm CMOS technology with the supply voltage of 1.2 V and sampling frequency of 500 MHz using Cadence EDA tool. The simulation results show that the total power of 152.67 µw with the delay of 72.5 ps is obtained. It can be seen that the proposed dynamic comparator has significantly reduced both the power and delay time compared to the previous design.