High Speed Low Power CMOS Comparator using Forward Body Bias Technique in 0.13 µm Technology

Authors

  • Sohiful Anuar Zainol Murad School of Microelectronic Engineering, Universiti Malaysia Perlis, Arau, Perlis, Malaysia
  • Azizi Harun School of Microelectronic Engineering, Universiti Malaysia Perlis, Arau, Perlis, Malaysia
  • Muhammad Mahyiddin Ramli School of Microelectronic Engineering, Universiti Malaysia Perlis, Arau, Perlis, Malaysia
  • Mohd Nazrin Md Isa School of Microelectronic Engineering, Universiti Malaysia Perlis, Arau, Perlis, Malaysia
  • Rohana Sapawi Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Malaysia Sarawak, Sarawak, Malaysia

Keywords:

CMOS, Analog Design, Comparator, High Speed, Low Power,

Abstract

This paper presents the design of high speed and low power CMOS comparator using a forward body bias technique in 0.13-µm technology. Three types of CMOS comparators’ topologies have been designed in order to compare the performances of speed and power with the conventional comparator. Based on the analysis, the double-tail dynamic comparator is chosen since it shows better performance for high speed and low power. Therefore, a modified high-speed, low power double-tail dynamic comparator is proposed by using a forward body bias technique in order to reduce the supply voltage. The proposed dynamic comparator is implemented in Silterra 0.13-μm CMOS technology with the supply voltage of 1.2 V and sampling frequency of 500 MHz using Cadence EDA tool. The simulation results show that the total power of 152.67 µw with the delay of 72.5 ps is obtained. It can be seen that the proposed dynamic comparator has significantly reduced both the power and delay time compared to the previous design.

References

S.A.Z Murad, et al., “Design of a low-power CMOS operational amplifier with common-mode feedback for pipeline analog-to-digital converter applications,” Turkish J. of Electrical Engineering & Computer Science, vol. 25, pp. 1908-1921, 2017.

Ishak, Izatul Syafina, Sohiful Anuar Zainol Murad, and Mohd Fairus Ahmad. "Low power folded cascode CMOS operational amplifier with common mode feedback for pipeline ADC," in Proc. Int. Integrated Engineering Summit (IIES2014) (2014): 1-4.

Jali, Mohd Hafiz. "Design of Gain Booster for Sample and Hold Stage of High Speed-Low Power Pipelined Analog-To-Digital Converter," J. of Telecommunication, Electronic and Computer Engineering (JTEC), vo. 5, no. 1, pp. 23-29, 2013.

Murad, S. A. Z., Muhammad M. Ramli, A. Azizan, M. N. M. Isa, and I. S. Ishak. "Low Power CMOS Operational Amplifier with Integrated Common-Mode Feedback for Data Converter," In MATEC Web of Conf., vol. 97, p. 01046. EDP Sciences, 2017.

Ata Khorami and Mohammad Sharifkhani, “High-speed low-power comparator for analog to digital converters,” AEU – Int. J. of Electronic and Communication, vol. 70, pp 886-894, 2016.

Veepsa Bhatia, et. al., “High speed power efficient CMOS inverter based current comparator in UMC 90 nm technology,” Int. J. of Electrical and Computer Engineering (IJECE), vol 6, pp. 90-98, Feb. 2016.

A Khorami, et. al., “A low-power high-speed comparator for analog to digital converters,” in Proc. IEEE Int. Symposium on Circuits and Systems, 2016, pp. 2010-2013.

Hugues J. Achigui, et. al., “Low-voltage, high-speed CMOS analog latched voltage comparator using the flipped voltage follower as input stage,” Microelectronic J., vol. 42, pp.785-789, 2011.

Roshani Gupta, et. al., “Design of high speed and low power 4-bit comparator using FGMOS,” AEU – Int. J. of Electronic and Communication, vol. 76, pp. 125-131, 2017.

L. F. Rahman, et. al., “Design of high speed and low offset dynamic latch comparator in 0.18 µm CMOS Process,” PloS one, vol. 9, pp. 1- 12, 2014.

J. R. Wu, et. al., “A preamplifier-latch comparator with reduced delay time for high accuracy switched-capacitor pipelined ADC,” Applied Mechanics and Materials, vol. 303, pp. 1842-1848, 2013.

I.S.A. Halim, et. al., “Low power CMOS charge sharing dynamic latch comparator using 0.18-μm technology,” in Proc. IEEE Regional Symposium on Micro and Nano Electronics. 2011.

R. M. N. H. R. Daud, et. al., “Design and analysis of low power and high speed dynamic latch comparator in 0.18 µm CMOS process,” Int. J. of Information and Electronic Engineering, vol. 2, pp. 944-947, 2012.

Samaneh Babayan-Mashhadi and Reza Lotfi, “Analysis and design of a low-voltage low-power double-tail comparator,” IEEE Trans. on Very Large Scale Integrated (VLSI) System, vol. 22, pp.353-352, 2014.

N. I. M. Azizi and S.H. Ruslan, “Design of a low power 0.25 µm CMOS comparator for sigma-delta analog-to-digital converter,” in Proc. IEEE Student Conf. on Research and Development (SCOReD), 2015, pp. 638-642.

A. Lahariya and A. Gupta, “Design of low power and high speed dynamic latch comparator using 180 nm technology,” in Proc. 2015 Int. Conf. on Signal Processing, Computing and Control, 2015.

V. Deepika and Sangeeta Singh, “Design and implementation of a lowpower, high-speed comparator,” in Procedia Materials Science, 2015, pp. 314-322.

S.A. Halim, et. al., “Rahim, Low power CMOS charge sharing dynamic latch comparator using 0.18-μm technology,” in Proc. IEEE Regional Symposium on Micro and Nano Electronics. 2011.

Mohsen Hassanpourghadi, et. al., “A low-power low-offset dynamic comparator for analog to digital converters,” Microelectronic J., vol. 45, pp. 256-262, 2014.

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Published

2018-08-28

How to Cite

Zainol Murad, S. A., Harun, A., Ramli, M. M., Md Isa, M. N., & Sapawi, R. (2018). High Speed Low Power CMOS Comparator using Forward Body Bias Technique in 0.13 µm Technology. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 10(3), 25–29. Retrieved from https://jtec.utem.edu.my/jtec/article/view/3440

Issue

Vol. 10 No. 3: July - September 2018

Section

Articles

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