Design of High Performance Packet Classification Architecture for Communication Networks

Authors

  • Ausaf Umar Khan Department of Electronics and Telecommunication, Anjuman College of Engineering and Technology, Nagpur, India.
  • Manish Chawhan Department of Electronics and Telecommunication Engineering, YCCE, Nagpur, India.
  • Yogesh Suryawanshi Department of Electronics and Communication Engineering, DMIETR, Wardha, India.
  • Sandeep Kakde Department of Electronics Engineering, YCCE, Nagpur, India

Keywords:

Firewall, Network Intrusion Detection System, Packet Classification, Quality Of Services,

Abstract

Packet classification is a crucial technique for secure communication and networking. Security tools and internet services use packet classification technique which involves checking of packets against predefined rules stored in a classifier. The performance of the available software solutions of classification is not desirable and efficient for wire speed processing in high speed networks. Ternary Content Addressable Memory (TCAM), Bit-Vector (BV), field split bit vector (FSBV) and StrideBV algorithm are hardware based packet classification algorithms. In this paper, simple and memory efficient approach for packet classification has been proposed using Xnor gate instead of using lookup tables called XnorBV approach. Packet header fields of Internet protocol (IP) addresses and protocol layer are classified using Xnor gate against predefined ruleset which also support ternary bit pattern of ‘1’, ‘0’ and ‘*’ while port numbers of packet header support range match by comparing port numbers against lower bound and upper bound. The proposed parallel pipelined architecture can sustain a high throughput of +100 Gbps and low latency. The proposed method is memory efficient than other existing techniques, also supports prefix, range and exact match without use of range to prefix conversion. Also proposed XnorBV architecture is independent of ruleset feature and supports multiple dimension classification.

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Published

2017-12-30

How to Cite

Khan, A. U., Chawhan, M., Suryawanshi, Y., & Kakde, S. (2017). Design of High Performance Packet Classification Architecture for Communication Networks. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 9(4), 109–115. Retrieved from https://jtec.utem.edu.my/jtec/article/view/2132

Issue

Vol. 9 No. 4: October - December 2017

Section

Articles

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