Low Power Design of MPPT Circuit Using Power Down System in 65nm CMOS Process

Authors

  • Gesille S. Rible Microelectronics Laboratory, EECE Department, Mindanao State University – Iligan Institute of Technology Iligan City, 9200 Philippines
  • Ma. Concepcion I. Sabate Microelectronics Laboratory, EECE Department, Mindanao State University – Iligan Institute of Technology Iligan City, 9200 Philippines
  • Jefferson A. Hora Microelectronics Laboratory, EECE Department, Mindanao State University – Iligan Institute of Technology Iligan City, 9200 Philippines

Keywords:

Fractional Open Circuit Voltage, Indoor Light Energy Harvesting, Maximum Power Point Tracking, Photovoltaic Cell,

Abstract

In the field of light energy harvesting, a great amount of power is wasted when the voltage of the photovoltaic cells does not reach the maximum power point at which the storage will charge at its most efficient manner. The most common solution is to build a maximum power point tracking (MPPT) circuit. However, this still needs improvement with very low energy produced indoor. Thus, aiming to reduce the power consumption of the conventional MPPT system, this study implemented a power down system that turns off idle blocks; hence, improving the performance of the conventional MPPT circuit. From several MPPT techniques, this study implemented the Fractional Open Circuit Voltage Method (FOCV), which has a lower cost and simple circuitry, neglecting the use of a microcontroller. Conventional FOCV-based MPPT systems are composed of a sampling circuit that sets the maximum power point voltage (VMPP) from the sampled open circuit voltage (VOC); and a comparator which assures that the accurate VMPP is stored at the output. From the simulation results, the conventional MPPT consumed a power of 324µW from the PV cell, which is higher than the 255µW consumed by this system. Therefore, the implementation of a power down system saved 21.2% more power than that of the conventional FOCV-based MPPT system. The size of the overall layout implemented in 65nm CMOS technology is 70.955 µm x 34.09 µm.

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Published

2018-01-15

How to Cite

S. Rible, G., Sabate, M. C. I., & Hora, J. A. (2018). Low Power Design of MPPT Circuit Using Power Down System in 65nm CMOS Process. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 10(1), 45–50. Retrieved from https://jtec.utem.edu.my/jtec/article/view/1933

Issue

Vol. 10 No. 1: January - March 2018

Section

Articles

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