1.
H.R A, Byrareddy CR, C. P N. Design of an Efficient AXI-4 Protocol for High Speed SOC Applications on FPGA Platform. JTEC [Internet]. 2020Aug.30 [cited 2024Apr.26];12(3):61-8. Available from: https://jtec.utem.edu.my/jtec/article/view/5774