Kaharudin K, Salehuddin F, Zain A, A. Aziz M. Implementation of Taguchi Method for Lower Drain Induced Barrier Lowering in Vertical Double Gate NMOS Device. JTEC [Internet]. 2016Jul.1 [cited 2024Apr.19];8(4):11-6. Available from: https://jtec.utem.edu.my/jtec/article/view/1196