Kaharudin, K.E., F. Salehuddin, A.S.M. Zain, and M.N.I A. Aziz. “Implementation of Taguchi Method for Lower Drain Induced Barrier Lowering in Vertical Double Gate NMOS Device”. Journal of Telecommunication, Electronic and Computer Engineering (JTEC) 8, no. 4 (July 1, 2016): 11–16. Accessed November 21, 2024. https://jtec.utem.edu.my/jtec/article/view/1196.