Haron, N.Z, A.M Darsono, and A.A M.Isa. “High Performance, Fault Tolerance Architecture for Reliable Hybrid Nanometric Memories”. Journal of Telecommunication, Electronic and Computer Engineering (JTEC) 4, no. 2 (December 1, 2012): 1–10. Accessed July 3, 2024. https://jtec.utem.edu.my/jtec/article/view/430.