Hashizume, M., Y. Shiraishi, H. Yotsuyanagi, H. Yokoyama, T. Tada, and S.-K. Lu. “Electrical Test of Resistive and Capacitive Open Defects at Data Bus in 3D Memory IC”. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), vol. 9, no. 3-2, Oct. 2017, pp. 39-42, https://jtec.utem.edu.my/jtec/article/view/2810.