Ahmataku, H., Mohamaddan, S., Warren, E., Yusuf, M., Alias, A. A., Abdul Manas, N. H. and Kipli, K. (2018) “Analysis of Gate Poly Delayering in SOI Wafer”, Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 10(1-12), pp. 85–87. Available at: https://jtec.utem.edu.my/jtec/article/view/3831 (Accessed: 5May2024).