Kaharudin, K., Salehuddin, F., Zain, A. and A. Aziz, M. (2016) “Implementation of Taguchi Method for Lower Drain Induced Barrier Lowering in Vertical Double Gate NMOS Device”, Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 8(4), pp. 11–16. Available at: https://jtec.utem.edu.my/jtec/article/view/1196 (Accessed: 21November2024).